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https://github.com/RGBCube/serenity
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Kernel: Support all Intel-defined extended CPUID feature flags for EAX=7
We're now able to detect all the extended CPUID feature flags from EBX/ECX/EDX for EAX=7 :^)
This commit is contained in:
Linus Groh
Andreas Kling
parent
6ca03b915e
commit
96e6420d8d
3 changed files with 405 additions and 12 deletions
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@ -37,7 +37,7 @@ private:
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u32 m_edx { 0xffffffff };
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};
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AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u128,
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AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u256,
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/* EAX=1, ECX */ //
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SSE3 = CPUFeature(1u) << 0u, // Streaming SIMD Extensions 3
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PCLMULQDQ = CPUFeature(1u) << 1u, // PCLMULDQ Instruction
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@ -105,20 +105,105 @@ AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u128,
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IA64 = CPUFeature(1u) << 62u, // IA64 processor emulating x86
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PBE = CPUFeature(1u) << 63u, // Pending Break Enable
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/* EAX=7, EBX */ //
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SMEP = CPUFeature(1u) << 64u, // Supervisor Mode Execution Protection
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RDSEED = CPUFeature(1u) << 65u, // RDSEED Instruction
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SMAP = CPUFeature(1u) << 66u, // Supervisor Mode Access Prevention
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FSGSBASE = CPUFeature(1u) << 64u, // Access to base of %fs and %gs
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TSC_ADJUST = CPUFeature(1u) << 65u, // IA32_TSC_ADJUST MSR
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SGX = CPUFeature(1u) << 66u, // Software Guard Extensions
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BMI1 = CPUFeature(1u) << 67u, // Bit Manipulation Instruction Set 1
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HLE = CPUFeature(1u) << 68u, // TSX Hardware Lock Elision
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AVX2 = CPUFeature(1u) << 69u, // Advanced Vector Extensions 2
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FDP_EXCPTN_ONLY = CPUFeature(1u) << 70u, // FDP_EXCPTN_ONLY
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SMEP = CPUFeature(1u) << 71u, // Supervisor Mode Execution Protection
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BMI2 = CPUFeature(1u) << 72u, // Bit Manipulation Instruction Set 2
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ERMS = CPUFeature(1u) << 73u, // Enhanced REP MOVSB/STOSB
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INVPCID = CPUFeature(1u) << 74u, // INVPCID Instruction
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RTM = CPUFeature(1u) << 75u, // TSX Restricted Transactional Memory
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PQM = CPUFeature(1u) << 76u, // Platform Quality of Service Monitoring
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ZERO_FCS_FDS = CPUFeature(1u) << 77u, // FPU CS and FPU DS deprecated
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MPX = CPUFeature(1u) << 78u, // Intel MPX (Memory Protection Extensions)
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PQE = CPUFeature(1u) << 79u, // Platform Quality of Service Enforcement
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AVX512_F = CPUFeature(1u) << 80u, // AVX-512 Foundation
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AVX512_DQ = CPUFeature(1u) << 81u, // AVX-512 Doubleword and Quadword Instructions
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RDSEED = CPUFeature(1u) << 82u, // RDSEED Instruction
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ADX = CPUFeature(1u) << 83u, // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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SMAP = CPUFeature(1u) << 84u, // Supervisor Mode Access Prevention
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AVX512_IFMA = CPUFeature(1u) << 85u, // AVX-512 Integer Fused Multiply-Add Instructions
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PCOMMIT = CPUFeature(1u) << 86u, // PCOMMIT Instruction
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CLFLUSHOPT = CPUFeature(1u) << 87u, // CLFLUSHOPT Instruction
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CLWB = CPUFeature(1u) << 88u, // CLWB Instruction
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INTEL_PT = CPUFeature(1u) << 89u, // Intel Processor Tracing
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AVX512_PF = CPUFeature(1u) << 90u, // AVX-512 Prefetch Instructions
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AVX512_ER = CPUFeature(1u) << 91u, // AVX-512 Exponential and Reciprocal Instructions
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AVX512_CD = CPUFeature(1u) << 92u, // AVX-512 Conflict Detection Instructions
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SHA = CPUFeature(1u) << 93u, // Intel SHA Extensions
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AVX512_BW = CPUFeature(1u) << 94u, // AVX-512 Byte and Word Instructions
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AVX512_VL = CPUFeature(1u) << 95u, // AVX-512 Vector Length Extensions
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/* EAX=7, ECX */ //
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UMIP = CPUFeature(1u) << 67u, // User-Mode Instruction Prevention
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PREFETCHWT1 = CPUFeature(1u) << 96u, // PREFETCHWT1 Instruction
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AVX512_VBMI = CPUFeature(1u) << 97u, // AVX-512 Vector Bit Manipulation Instructions
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UMIP = CPUFeature(1u) << 98u, // UMIP
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PKU = CPUFeature(1u) << 99u, // Memory Protection Keys for User-mode pages
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OSPKU = CPUFeature(1u) << 100u, // PKU enabled by OS
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WAITPKG = CPUFeature(1u) << 101u, // Timed pause and user-level monitor/wait
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AVX512_VBMI2 = CPUFeature(1u) << 102u, // AVX-512 Vector Bit Manipulation Instructions 2
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CET_SS = CPUFeature(1u) << 103u, // Control Flow Enforcement (CET) Shadow Stack
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GFNI = CPUFeature(1u) << 104u, // Galois Field Instructions
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VAES = CPUFeature(1u) << 105u, // Vector AES instruction set (VEX-256/EVEX)
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VPCLMULQDQ = CPUFeature(1u) << 106u, // CLMUL instruction set (VEX-256/EVEX)
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AVX512_VNNI = CPUFeature(1u) << 107u, // AVX-512 Vector Neural Network Instructions
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AVX512_BITALG = CPUFeature(1u) << 108u, // AVX-512 BITALG Instructions
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TME_EN = CPUFeature(1u) << 109u, // IA32_TME related MSRs are supported
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AVX512_VPOPCNTDQ = CPUFeature(1u) << 110u, // AVX-512 Vector Population Count Double and Quad-word
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/* ECX Bit 15 */ // Reserved
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INTEL_5_LEVEL_PAGING = CPUFeature(1u) << 112u, // Intel 5-Level Paging
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RDPID = CPUFeature(1u) << 113u, // RDPID Instruction
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KL = CPUFeature(1u) << 114u, // Key Locker
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/* ECX Bit 24 */ // Reserved
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CLDEMOTE = CPUFeature(1u) << 116u, // Cache Line Demote
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/* ECX Bit 26 */ // Reserved
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MOVDIRI = CPUFeature(1u) << 118u, // MOVDIRI Instruction
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MOVDIR64B = CPUFeature(1u) << 119u, // MOVDIR64B Instruction
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ENQCMD = CPUFeature(1u) << 120u, // ENQCMD Instruction
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SGX_LC = CPUFeature(1u) << 121u, // SGX Launch Configuration
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PKS = CPUFeature(1u) << 122u, // Protection Keys for Supervisor-Mode Pages
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/* EAX=7, EDX */ //
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/* ECX Bit 0-1 */ // Reserved
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AVX512_4VNNIW = CPUFeature(1u) << 125u, // AVX-512 4-register Neural Network Instructions
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AVX512_4FMAPS = CPUFeature(1u) << 126u, // AVX-512 4-register Multiply Accumulation Single precision
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FSRM = CPUFeature(1u) << 127u, // Fast Short REP MOVSB
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/* ECX Bit 5-7 */ // Reserved
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AVX512_VP2INTERSECT = CPUFeature(1u) << 131u, // AVX-512 VP2INTERSECT Doubleword and Quadword Instructions
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SRBDS_CTRL = CPUFeature(1u) << 132u, // Special Register Buffer Data Sampling Mitigations
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MD_CLEAR = CPUFeature(1u) << 133u, // VERW instruction clears CPU buffers
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RTM_ALWAYS_ABORT = CPUFeature(1u) << 134u, // All TSX transactions are aborted
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/* ECX Bit 12 */ // Reserved
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TSX_FORCE_ABORT = CPUFeature(1u) << 136u, // TSX_FORCE_ABORT MSR
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SERIALIZE = CPUFeature(1u) << 137u, // Serialize instruction execution
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HYBRID = CPUFeature(1u) << 138u, // Mixture of CPU types in processor topology
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TSXLDTRK = CPUFeature(1u) << 139u, // TSX suspend load address tracking
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/* ECX Bit 17 */ // Reserved
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PCONFIG = CPUFeature(1u) << 141u, // Platform configuration (Memory Encryption Technologies Instructions)
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LBR = CPUFeature(1u) << 142u, // Architectural Last Branch Records
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CET_IBT = CPUFeature(1u) << 143u, // Control flow enforcement (CET) indirect branch tracking
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/* ECX Bit 21 */ // Reserved
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AMX_BF16 = CPUFeature(1u) << 145u, // Tile computation on bfloat16 numbers
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AVX512_FP16 = CPUFeature(1u) << 146u, // AVX512-FP16 half-precision floating-point instructions
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AMX_TILE = CPUFeature(1u) << 147u, // Tile architecture
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AMX_INT8 = CPUFeature(1u) << 148u, // Tile computation on 8-bit integers
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SPEC_CTRL = CPUFeature(1u) << 149u, // Speculation Control
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STIBP = CPUFeature(1u) << 150u, // Single Thread Indirect Branch Predictor
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L1D_FLUSH = CPUFeature(1u) << 151u, // IA32_FLUSH_CMD MSR
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IA32_ARCH_CAPABILITIES = CPUFeature(1u) << 152u, // IA32_ARCH_CAPABILITIES MSR
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IA32_CORE_CAPABILITIES = CPUFeature(1u) << 153u, // IA32_CORE_CAPABILITIES MSR
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SSBD = CPUFeature(1u) << 154u, // Speculative Store Bypass Disable
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/* EAX=80000001h, EDX */ //
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SYSCALL = CPUFeature(1u) << 68u, // SYSCALL/SYSRET Instructions
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NX = CPUFeature(1u) << 69u, // NX bit
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RDTSCP = CPUFeature(1u) << 70u, // RDTSCP Instruction
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LM = CPUFeature(1u) << 71u, // Long Mode
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SYSCALL = CPUFeature(1u) << 155u, // SYSCALL/SYSRET Instructions
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NX = CPUFeature(1u) << 156u, // NX bit
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RDTSCP = CPUFeature(1u) << 157u, // RDTSCP Instruction
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LM = CPUFeature(1u) << 158u, // Long Mode
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/* EAX=80000007h, EDX */ //
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CONSTANT_TSC = CPUFeature(1u) << 72u, // Invariant TSC
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NONSTOP_TSC = CPUFeature(1u) << 73u, // Invariant TSC
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__End = CPUFeature(1u) << 127u);
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CONSTANT_TSC = CPUFeature(1u) << 159u, // Invariant TSC
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NONSTOP_TSC = CPUFeature(1u) << 160u, // Invariant TSC
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__End = CPUFeature(1u) << 255u);
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StringView cpu_feature_to_string_view(CPUFeature::Type const&);
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