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Everywhere: Change all XXX into FIXME or remove as appropriate

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This commit is contained in:
Ben Wiederhake 2023-02-15 21:31:00 +01:00 • committed by Jelle Raaijmakers
parent 00c21c5424
commit 9a7b3c145f
4 changed files with 10 additions and 10 deletions
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8
Kernel/Arch/aarch64/CPUID.cpp
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@ -196,11 +196,11 @@ CPUFeature::Type detect_cpu_features()
features |= CPUFeature::MTE3;
if (processor_feature_register_1.MTE >= 0b0010 && processor_feature_register_1.MTEX == 0b0001) {
features |= CPUFeature::MTE4;
features |= CPUFeature::MTE_CANONICAL_TAGS; // XXX: not really explicit in the spec
features |= CPUFeature::MTE_NO_ADDRESS_TAGS; // XXX: not really explicit in the spec
features |= CPUFeature::MTE_CANONICAL_TAGS; // FIXME: not really explicit in the spec
features |= CPUFeature::MTE_NO_ADDRESS_TAGS; // FIXME: not really explicit in the spec
}
if (processor_feature_register_1.MTE >= 0b0011 && processor_feature_register_1.MTE_frac == 0b0000)
features |= CPUFeature::MTE_ASYM_FAULT; // XXX: not really explicit in the spec
features |= CPUFeature::MTE_ASYM_FAULT; // FIXME: not really explicit in the spec
if (processor_feature_register_1.SME == 0b0010)
features |= CPUFeature::SME2;
if (processor_feature_register_1.RNDR_trap == 0b0001)
@ -427,7 +427,7 @@ CPUFeature::Type detect_cpu_features()
features |= CPUFeature::BRBE;
if (debug_feature_register_0.BRBE == 0b0010)
features |= CPUFeature::BRBEv1p1;
if (debug_feature_register_0.ExtTrcBuff == 0b0001 && features.has_flag(CPUFeature::TRBE)) // XXX: order-dependent!
if (debug_feature_register_0.ExtTrcBuff == 0b0001 && features.has_flag(CPUFeature::TRBE)) // FIXME: order-dependent!
features |= CPUFeature::TRBE_EXT;
if (debug_feature_register_0.HPMN0 == 0b0001)
features |= CPUFeature::HPMN0;

2
Kernel/Arch/aarch64/CPUID.h
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@ -270,7 +270,7 @@ AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u256,
TRBE = CPUFeature(1u) << 239u, // Trace Buffer Extension
SME = CPUFeature(1u) << 240u, // Scalable Matrix Extension
__End = CPUFeature(1u) << 255u); // XXX — SENTINEL VALUE — XXX
__End = CPUFeature(1u) << 255u); // SENTINEL VALUE
enum class ArmLimited { // 0x41
Cortex_A34 = 0xd02,