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Kernel: Add the DeviceController class in the PCI subsystem
Such device is not an IRQHandler by itself, but actually a controller of many IRQ or MSI devices. The purpose of this class is to manage multiple sources of interrupts. For example, a generic ISA IDE controller controls 2 IRQ sources - 14 and 15. So, when we initialize the IDE controller, it will initialize two IDE channels (also known as PATAChannels) to utilize IRQ 14 and 15, respectively. NVMe with MSI-X support can theoretically handle up to 2048 interrupts.
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@ -83,6 +83,7 @@ set(KERNEL_SOURCES
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Net/UDPSocket.cpp
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PCI/Access.cpp
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PCI/Device.cpp
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PCI/DeviceController.cpp
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PCI/IOAccess.cpp
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PCI/Initializer.cpp
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PCI/MMIOAccess.cpp
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