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Kernel: Add the DeviceController class in the PCI subsystem

Such device is not an IRQHandler by itself, but actually a controller of
many IRQ or MSI devices. The purpose of this class is to manage multiple
sources of interrupts.

For example, a generic ISA IDE controller controls 2 IRQ sources - 14
and 15. So, when we initialize the IDE controller, it will initialize
two IDE channels (also known as PATAChannels) to utilize IRQ 14 and 15,
respectively. NVMe with MSI-X support can theoretically handle up to
2048 interrupts.
This commit is contained in:
Liav A 2020-12-18 10:52:52 +02:00 committed by Andreas Kling
parent f1d7d864ae
commit 9d10eb473d
4 changed files with 86 additions and 0 deletions

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@ -83,6 +83,7 @@ set(KERNEL_SOURCES
Net/UDPSocket.cpp
PCI/Access.cpp
PCI/Device.cpp
PCI/DeviceController.cpp
PCI/IOAccess.cpp
PCI/Initializer.cpp
PCI/MMIOAccess.cpp