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Kernel: Move all Graphics-related code into Devices/GPU directory
Like the HID, Audio and Storage subsystem, the Graphics subsystem (which handles GPUs technically) exposes unix device files (typically in /dev). To ensure consistency across the repository, move all related files to a new directory under Kernel/Devices called "GPU". Also remove the redundant "GPU" word from the VirtIO driver directory, and the word "Graphics" from GraphicsManagement.{h,cpp} filenames.
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69 changed files with 167 additions and 167 deletions
70
Kernel/Devices/GPU/Intel/Plane/DisplayPlane.cpp
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Kernel/Devices/GPU/Intel/Plane/DisplayPlane.cpp
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/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Devices/GPU/Intel/Plane/DisplayPlane.h>
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#include <Kernel/Memory/PhysicalAddress.h>
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namespace Kernel {
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IntelDisplayPlane::IntelDisplayPlane(Memory::TypedMapping<PlaneRegisters volatile> plane_registers_mapping)
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: m_plane_registers(move(plane_registers_mapping))
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{
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}
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IntelDisplayPlane::ShadowRegisters IntelDisplayPlane::shadow_registers() const
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{
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SpinlockLocker locker(m_access_lock);
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return m_shadow_registers;
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}
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ErrorOr<void> IntelDisplayPlane::set_horizontal_active_pixels_count(Badge<IntelDisplayConnectorGroup>, size_t horizontal_active_pixels_count)
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{
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SpinlockLocker locker(m_access_lock);
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m_horizontal_active_pixels_count = horizontal_active_pixels_count;
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return {};
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}
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ErrorOr<void> IntelDisplayPlane::set_vertical_active_pixels_count(Badge<IntelDisplayConnectorGroup>, size_t vertical_active_pixels_count)
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{
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SpinlockLocker locker(m_access_lock);
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m_vertical_active_pixels_count = vertical_active_pixels_count;
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return {};
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}
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ErrorOr<void> IntelDisplayPlane::set_horizontal_stride(Badge<IntelDisplayConnectorGroup>, size_t horizontal_stride)
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{
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SpinlockLocker locker(m_access_lock);
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m_horizontal_stride = horizontal_stride;
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return {};
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}
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ErrorOr<void> IntelDisplayPlane::set_aperture_base(Badge<IntelDisplayConnectorGroup>, PhysicalAddress aperture_start)
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{
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SpinlockLocker locker(m_access_lock);
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m_aperture_start.set(aperture_start.get());
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return {};
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}
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ErrorOr<void> IntelDisplayPlane::set_pipe(Badge<IntelDisplayConnectorGroup>, PipeSelect pipe_select)
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{
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SpinlockLocker locker(m_access_lock);
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m_pipe_select = pipe_select;
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return {};
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}
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bool IntelDisplayPlane::is_enabled(Badge<IntelDisplayConnectorGroup>)
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{
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SpinlockLocker locker(m_access_lock);
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return m_shadow_registers.control & (1 << 31);
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}
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ErrorOr<void> IntelDisplayPlane::disable(Badge<IntelDisplayConnectorGroup>)
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{
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SpinlockLocker locker(m_access_lock);
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// Note: We use the shadow register so we don't have the already set
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// settings being lost.
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m_shadow_registers.control &= ~(1 << 31);
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m_plane_registers->control = m_shadow_registers.control;
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return {};
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}
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}
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77
Kernel/Devices/GPU/Intel/Plane/DisplayPlane.h
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Kernel/Devices/GPU/Intel/Plane/DisplayPlane.h
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/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/RefPtr.h>
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#include <AK/Try.h>
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#include <AK/Types.h>
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#include <Kernel/Devices/GPU/DisplayConnector.h>
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#include <Kernel/Devices/GPU/Intel/Definitions.h>
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#include <Kernel/Locking/Spinlock.h>
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#include <Kernel/Memory/TypedMapping.h>
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namespace Kernel {
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class IntelDisplayConnectorGroup;
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class IntelDisplayPlane {
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public:
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enum class PipeSelect {
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PipeA,
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PipeB,
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PipeC,
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PipeD,
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};
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// Note: This is used to "cache" all the registers we wrote to, because
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// we might not be able to read them directly from hardware later.
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struct ShadowRegisters {
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u32 control;
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u32 linear_offset;
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u32 stride;
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u32 surface_base;
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};
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public:
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static ErrorOr<NonnullOwnPtr<IntelDisplayPlane>> create_with_physical_address(PhysicalAddress plane_registers_start_address);
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ErrorOr<void> set_horizontal_active_pixels_count(Badge<IntelDisplayConnectorGroup>, size_t horizontal_active_pixels_count);
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ErrorOr<void> set_vertical_active_pixels_count(Badge<IntelDisplayConnectorGroup>, size_t vertical_active_pixels_count);
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ErrorOr<void> set_horizontal_stride(Badge<IntelDisplayConnectorGroup>, size_t horizontal_stride);
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ErrorOr<void> set_aperture_base(Badge<IntelDisplayConnectorGroup>, PhysicalAddress aperture_start);
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ErrorOr<void> set_pipe(Badge<IntelDisplayConnectorGroup>, PipeSelect);
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virtual ErrorOr<void> enable(Badge<IntelDisplayConnectorGroup>) = 0;
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bool is_enabled(Badge<IntelDisplayConnectorGroup>);
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ErrorOr<void> disable(Badge<IntelDisplayConnectorGroup>);
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ShadowRegisters shadow_registers() const;
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virtual ~IntelDisplayPlane() = default;
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protected:
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struct [[gnu::packed]] PlaneRegisters {
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u32 control;
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u32 linear_offset;
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u32 stride;
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u8 padding[24]; // Note: This might contain other registers, don't touch them.
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u32 surface_base;
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};
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explicit IntelDisplayPlane(Memory::TypedMapping<PlaneRegisters volatile> registers_mapping);
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mutable Spinlock<LockRank::None> m_access_lock;
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ShadowRegisters m_shadow_registers {};
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Memory::TypedMapping<PlaneRegisters volatile> m_plane_registers;
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// Note: The PipeSelect value is used only in planes until Skylake graphics.
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PipeSelect m_pipe_select { PipeSelect::PipeA };
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PhysicalAddress m_aperture_start;
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size_t m_horizontal_stride { 0 };
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size_t m_horizontal_active_pixels_count { 0 };
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size_t m_vertical_active_pixels_count { 0 };
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};
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}
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60
Kernel/Devices/GPU/Intel/Plane/G33DisplayPlane.cpp
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60
Kernel/Devices/GPU/Intel/Plane/G33DisplayPlane.cpp
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/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Devices/GPU/Intel/Plane/G33DisplayPlane.h>
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#include <Kernel/Memory/PhysicalAddress.h>
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namespace Kernel {
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ErrorOr<NonnullOwnPtr<IntelG33DisplayPlane>> IntelG33DisplayPlane::create_with_physical_address(PhysicalAddress plane_registers_start_address)
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{
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auto registers_mapping = TRY(Memory::map_typed<PlaneRegisters volatile>(plane_registers_start_address, sizeof(PlaneRegisters), Memory::Region::Access::ReadWrite));
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return adopt_nonnull_own_or_enomem(new (nothrow) IntelG33DisplayPlane(move(registers_mapping)));
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}
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IntelG33DisplayPlane::IntelG33DisplayPlane(Memory::TypedMapping<PlaneRegisters volatile> registers_mapping)
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: IntelDisplayPlane(move(registers_mapping))
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{
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}
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ErrorOr<void> IntelG33DisplayPlane::enable(Badge<IntelDisplayConnectorGroup>)
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{
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SpinlockLocker locker(m_access_lock);
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VERIFY(((m_horizontal_active_pixels_count * 4) % 64 == 0));
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VERIFY(((m_horizontal_stride) % 64 == 0));
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u32 control_value = 0;
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switch (m_pipe_select) {
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case PipeSelect::PipeA:
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control_value |= (0b00 << 24);
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break;
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case PipeSelect::PipeB:
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control_value |= (0b01 << 24);
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break;
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case PipeSelect::PipeC:
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control_value |= (0b10 << 24);
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break;
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case PipeSelect::PipeD:
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control_value |= (0b11 << 24);
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break;
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}
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// Note: Set the plane to work with 32 bit BGRX (Ignore Alpha channel).
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// Note: Bit 31 is set to turn on the plane.
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control_value |= (0b0110 << 26) | (1 << 31);
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m_plane_registers->stride = m_horizontal_stride;
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m_shadow_registers.stride = m_horizontal_stride;
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m_plane_registers->linear_offset = 0;
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m_shadow_registers.linear_offset = 0;
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m_plane_registers->surface_base = m_aperture_start.get();
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m_shadow_registers.surface_base = m_aperture_start.get();
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m_plane_registers->control = control_value;
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m_shadow_registers.control = control_value;
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return {};
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}
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}
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26
Kernel/Devices/GPU/Intel/Plane/G33DisplayPlane.h
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Kernel/Devices/GPU/Intel/Plane/G33DisplayPlane.h
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/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/RefPtr.h>
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#include <AK/Try.h>
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#include <AK/Types.h>
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#include <Kernel/Devices/GPU/Intel/Plane/DisplayPlane.h>
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namespace Kernel {
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class IntelDisplayConnectorGroup;
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class IntelG33DisplayPlane final : public IntelDisplayPlane {
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public:
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static ErrorOr<NonnullOwnPtr<IntelG33DisplayPlane>> create_with_physical_address(PhysicalAddress plane_registers_start_address);
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virtual ErrorOr<void> enable(Badge<IntelDisplayConnectorGroup>) override;
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private:
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explicit IntelG33DisplayPlane(Memory::TypedMapping<volatile IntelDisplayPlane::PlaneRegisters> plane_registers_mapping);
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};
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}
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