Kernel: Move all Graphics-related code into Devices/GPU directory

Like the HID, Audio and Storage subsystem, the Graphics subsystem (which
handles GPUs technically) exposes unix device files (typically in /dev).
To ensure consistency across the repository, move all related files to a
new directory under Kernel/Devices called "GPU".

Also remove the redundant "GPU" word from the VirtIO driver directory,
and the word "Graphics" from GraphicsManagement.{h,cpp} filenames.

Kernel/Devices/GPU/Intel/Plane/DisplayPlane.cpp

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <Kernel/Devices/GPU/Intel/Plane/DisplayPlane.h>
+#include <Kernel/Memory/PhysicalAddress.h>
+
+namespace Kernel {
+
+IntelDisplayPlane::IntelDisplayPlane(Memory::TypedMapping<PlaneRegisters volatile> plane_registers_mapping)
+    : m_plane_registers(move(plane_registers_mapping))
+{
+}
+
+IntelDisplayPlane::ShadowRegisters IntelDisplayPlane::shadow_registers() const
+{
+    SpinlockLocker locker(m_access_lock);
+    return m_shadow_registers;
+}
+
+ErrorOr<void> IntelDisplayPlane::set_horizontal_active_pixels_count(Badge<IntelDisplayConnectorGroup>, size_t horizontal_active_pixels_count)
+{
+    SpinlockLocker locker(m_access_lock);
+    m_horizontal_active_pixels_count = horizontal_active_pixels_count;
+    return {};
+}
+ErrorOr<void> IntelDisplayPlane::set_vertical_active_pixels_count(Badge<IntelDisplayConnectorGroup>, size_t vertical_active_pixels_count)
+{
+    SpinlockLocker locker(m_access_lock);
+    m_vertical_active_pixels_count = vertical_active_pixels_count;
+    return {};
+}
+ErrorOr<void> IntelDisplayPlane::set_horizontal_stride(Badge<IntelDisplayConnectorGroup>, size_t horizontal_stride)
+{
+    SpinlockLocker locker(m_access_lock);
+    m_horizontal_stride = horizontal_stride;
+    return {};
+}
+ErrorOr<void> IntelDisplayPlane::set_aperture_base(Badge<IntelDisplayConnectorGroup>, PhysicalAddress aperture_start)
+{
+    SpinlockLocker locker(m_access_lock);
+    m_aperture_start.set(aperture_start.get());
+    return {};
+}
+ErrorOr<void> IntelDisplayPlane::set_pipe(Badge<IntelDisplayConnectorGroup>, PipeSelect pipe_select)
+{
+    SpinlockLocker locker(m_access_lock);
+    m_pipe_select = pipe_select;
+    return {};
+}
+
+bool IntelDisplayPlane::is_enabled(Badge<IntelDisplayConnectorGroup>)
+{
+    SpinlockLocker locker(m_access_lock);
+    return m_shadow_registers.control & (1 << 31);
+}
+
+ErrorOr<void> IntelDisplayPlane::disable(Badge<IntelDisplayConnectorGroup>)
+{
+    SpinlockLocker locker(m_access_lock);
+    // Note: We use the shadow register so we don't have the already set
+    // settings being lost.
+    m_shadow_registers.control &= ~(1 << 31);
+    m_plane_registers->control = m_shadow_registers.control;
+    return {};
+}
+
+}

Kernel/Devices/GPU/Intel/Plane/DisplayPlane.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <AK/RefPtr.h>
+#include <AK/Try.h>
+#include <AK/Types.h>
+#include <Kernel/Devices/GPU/DisplayConnector.h>
+#include <Kernel/Devices/GPU/Intel/Definitions.h>
+#include <Kernel/Locking/Spinlock.h>
+#include <Kernel/Memory/TypedMapping.h>
+
+namespace Kernel {
+
+class IntelDisplayConnectorGroup;
+class IntelDisplayPlane {
+public:
+    enum class PipeSelect {
+        PipeA,
+        PipeB,
+        PipeC,
+        PipeD,
+    };
+
+    // Note: This is used to "cache" all the registers we wrote to, because
+    // we might not be able to read them directly from hardware later.
+    struct ShadowRegisters {
+        u32 control;
+        u32 linear_offset;
+        u32 stride;
+        u32 surface_base;
+    };
+
+public:
+    static ErrorOr<NonnullOwnPtr<IntelDisplayPlane>> create_with_physical_address(PhysicalAddress plane_registers_start_address);
+
+    ErrorOr<void> set_horizontal_active_pixels_count(Badge<IntelDisplayConnectorGroup>, size_t horizontal_active_pixels_count);
+    ErrorOr<void> set_vertical_active_pixels_count(Badge<IntelDisplayConnectorGroup>, size_t vertical_active_pixels_count);
+    ErrorOr<void> set_horizontal_stride(Badge<IntelDisplayConnectorGroup>, size_t horizontal_stride);
+    ErrorOr<void> set_aperture_base(Badge<IntelDisplayConnectorGroup>, PhysicalAddress aperture_start);
+    ErrorOr<void> set_pipe(Badge<IntelDisplayConnectorGroup>, PipeSelect);
+
+    virtual ErrorOr<void> enable(Badge<IntelDisplayConnectorGroup>) = 0;
+    bool is_enabled(Badge<IntelDisplayConnectorGroup>);
+    ErrorOr<void> disable(Badge<IntelDisplayConnectorGroup>);
+
+    ShadowRegisters shadow_registers() const;
+
+    virtual ~IntelDisplayPlane() = default;
+
+protected:
+    struct [[gnu::packed]] PlaneRegisters {
+        u32 control;
+        u32 linear_offset;
+        u32 stride;
+        u8 padding[24]; // Note: This might contain other registers, don't touch them.
+        u32 surface_base;
+    };
+
+    explicit IntelDisplayPlane(Memory::TypedMapping<PlaneRegisters volatile> registers_mapping);
+    mutable Spinlock<LockRank::None> m_access_lock;
+    ShadowRegisters m_shadow_registers {};
+    Memory::TypedMapping<PlaneRegisters volatile> m_plane_registers;
+
+    // Note: The PipeSelect value is used only in planes until Skylake graphics.
+    PipeSelect m_pipe_select { PipeSelect::PipeA };
+
+    PhysicalAddress m_aperture_start;
+    size_t m_horizontal_stride { 0 };
+    size_t m_horizontal_active_pixels_count { 0 };
+    size_t m_vertical_active_pixels_count { 0 };
+};
+}

Kernel/Devices/GPU/Intel/Plane/G33DisplayPlane.cpp

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <Kernel/Devices/GPU/Intel/Plane/G33DisplayPlane.h>
+#include <Kernel/Memory/PhysicalAddress.h>
+
+namespace Kernel {
+
+ErrorOr<NonnullOwnPtr<IntelG33DisplayPlane>> IntelG33DisplayPlane::create_with_physical_address(PhysicalAddress plane_registers_start_address)
+{
+    auto registers_mapping = TRY(Memory::map_typed<PlaneRegisters volatile>(plane_registers_start_address, sizeof(PlaneRegisters), Memory::Region::Access::ReadWrite));
+    return adopt_nonnull_own_or_enomem(new (nothrow) IntelG33DisplayPlane(move(registers_mapping)));
+}
+
+IntelG33DisplayPlane::IntelG33DisplayPlane(Memory::TypedMapping<PlaneRegisters volatile> registers_mapping)
+    : IntelDisplayPlane(move(registers_mapping))
+{
+}
+
+ErrorOr<void> IntelG33DisplayPlane::enable(Badge<IntelDisplayConnectorGroup>)
+{
+    SpinlockLocker locker(m_access_lock);
+    VERIFY(((m_horizontal_active_pixels_count * 4) % 64 == 0));
+    VERIFY(((m_horizontal_stride) % 64 == 0));
+
+    u32 control_value = 0;
+
+    switch (m_pipe_select) {
+    case PipeSelect::PipeA:
+        control_value |= (0b00 << 24);
+        break;
+    case PipeSelect::PipeB:
+        control_value |= (0b01 << 24);
+        break;
+    case PipeSelect::PipeC:
+        control_value |= (0b10 << 24);
+        break;
+    case PipeSelect::PipeD:
+        control_value |= (0b11 << 24);
+        break;
+    }
+
+    // Note: Set the plane to work with 32 bit BGRX (Ignore Alpha channel).
+    // Note: Bit 31 is set to turn on the plane.
+    control_value |= (0b0110 << 26) | (1 << 31);
+
+    m_plane_registers->stride = m_horizontal_stride;
+    m_shadow_registers.stride = m_horizontal_stride;
+    m_plane_registers->linear_offset = 0;
+    m_shadow_registers.linear_offset = 0;
+    m_plane_registers->surface_base = m_aperture_start.get();
+    m_shadow_registers.surface_base = m_aperture_start.get();
+    m_plane_registers->control = control_value;
+    m_shadow_registers.control = control_value;
+    return {};
+}
+}

Kernel/Devices/GPU/Intel/Plane/G33DisplayPlane.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <AK/RefPtr.h>
+#include <AK/Try.h>
+#include <AK/Types.h>
+#include <Kernel/Devices/GPU/Intel/Plane/DisplayPlane.h>
+
+namespace Kernel {
+
+class IntelDisplayConnectorGroup;
+class IntelG33DisplayPlane final : public IntelDisplayPlane {
+public:
+    static ErrorOr<NonnullOwnPtr<IntelG33DisplayPlane>> create_with_physical_address(PhysicalAddress plane_registers_start_address);
+
+    virtual ErrorOr<void> enable(Badge<IntelDisplayConnectorGroup>) override;
+
+private:
+    explicit IntelG33DisplayPlane(Memory::TypedMapping<volatile IntelDisplayPlane::PlaneRegisters> plane_registers_mapping);
+};
+}