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https://github.com/RGBCube/serenity
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UserspaceEmulator: Implement the ROL/ROR/RCL/RCR instructions
This commit is contained in:
Andreas Kling
parent
897af8b4f7
commit
9f1221c785
2 changed files with 176 additions and 42 deletions
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@ -1555,24 +1555,100 @@ void SoftCPU::PUSH_reg32(const X86::Instruction& insn)
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}
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}
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void SoftCPU::RCL_RM16_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM32_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM32_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM8_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM8_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM8_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCR_RM16_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCR_RM16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCR_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCR_RM32_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCR_RM32_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCR_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCR_RM8_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCR_RM8_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCR_RM8_imm8(const X86::Instruction&) { TODO(); }
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template<typename T, bool cf>
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ALWAYS_INLINE static T op_rcl_impl(SoftCPU& cpu, T data, u8 steps)
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{
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if (steps == 0)
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return data;
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u32 result = 0;
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u32 new_flags = 0;
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if constexpr (cf)
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asm volatile("stc");
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else
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asm volatile("clc");
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if constexpr (sizeof(T) == 4) {
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asm volatile("rcll %%cl, %%eax\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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} else if constexpr (sizeof(T) == 2) {
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asm volatile("rclw %%cl, %%ax\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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} else if constexpr (sizeof(T) == 1) {
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asm volatile("rclb %%cl, %%al\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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}
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asm volatile(
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"pushf\n"
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"pop %%ebx"
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: "=b"(new_flags));
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cpu.set_flags_oc(new_flags);
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return result;
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}
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template<typename T>
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ALWAYS_INLINE static T op_rcl(SoftCPU& cpu, T data, u8 steps)
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{
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if (cpu.cf())
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return op_rcl_impl<T, true>(cpu, data, steps);
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return op_rcl_impl<T, false>(cpu, data, steps);
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}
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DEFINE_GENERIC_SHIFT_ROTATE_INSN_HANDLERS(RCL, op_rcl)
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template<typename T, bool cf>
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ALWAYS_INLINE static T op_rcr_impl(SoftCPU& cpu, T data, u8 steps)
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{
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if (steps == 0)
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return data;
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u32 result = 0;
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u32 new_flags = 0;
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if constexpr (cf)
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asm volatile("stc");
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else
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asm volatile("clc");
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if constexpr (sizeof(T) == 4) {
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asm volatile("rcrl %%cl, %%eax\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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} else if constexpr (sizeof(T) == 2) {
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asm volatile("rcrw %%cl, %%ax\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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} else if constexpr (sizeof(T) == 1) {
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asm volatile("rcrb %%cl, %%al\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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}
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asm volatile(
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"pushf\n"
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"pop %%ebx"
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: "=b"(new_flags));
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cpu.set_flags_oc(new_flags);
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return result;
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}
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template<typename T>
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ALWAYS_INLINE static T op_rcr(SoftCPU& cpu, T data, u8 steps)
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{
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if (cpu.cf())
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return op_rcr_impl<T, true>(cpu, data, steps);
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return op_rcr_impl<T, false>(cpu, data, steps);
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}
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DEFINE_GENERIC_SHIFT_ROTATE_INSN_HANDLERS(RCR, op_rcr)
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void SoftCPU::RDTSC(const X86::Instruction&) { TODO(); }
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void SoftCPU::RET(const X86::Instruction& insn)
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@ -1591,24 +1667,74 @@ void SoftCPU::RET_imm16(const X86::Instruction& insn)
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set_esp(esp() + insn.imm16());
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}
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void SoftCPU::ROL_RM16_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROL_RM16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROL_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROL_RM32_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROL_RM32_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROL_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROL_RM8_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROL_RM8_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROL_RM8_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROR_RM16_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROR_RM16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROR_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROR_RM32_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROR_RM32_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROR_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROR_RM8_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROR_RM8_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::ROR_RM8_imm8(const X86::Instruction&) { TODO(); }
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template<typename T>
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ALWAYS_INLINE static T op_rol(SoftCPU& cpu, T data, u8 steps)
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{
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if (steps == 0)
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return data;
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u32 result = 0;
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u32 new_flags = 0;
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if constexpr (sizeof(T) == 4) {
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asm volatile("roll %%cl, %%eax\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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} else if constexpr (sizeof(T) == 2) {
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asm volatile("rolw %%cl, %%ax\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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} else if constexpr (sizeof(T) == 1) {
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asm volatile("rolb %%cl, %%al\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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}
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asm volatile(
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"pushf\n"
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"pop %%ebx"
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: "=b"(new_flags));
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cpu.set_flags_oc(new_flags);
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return result;
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}
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DEFINE_GENERIC_SHIFT_ROTATE_INSN_HANDLERS(ROL, op_rol)
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template<typename T>
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ALWAYS_INLINE static T op_ror(SoftCPU& cpu, T data, u8 steps)
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{
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if (steps == 0)
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return data;
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u32 result = 0;
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u32 new_flags = 0;
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if constexpr (sizeof(T) == 4) {
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asm volatile("rorl %%cl, %%eax\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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} else if constexpr (sizeof(T) == 2) {
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asm volatile("rorw %%cl, %%ax\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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} else if constexpr (sizeof(T) == 1) {
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asm volatile("rorb %%cl, %%al\n"
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: "=a"(result)
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: "a"(data), "c"(steps));
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}
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asm volatile(
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"pushf\n"
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"pop %%ebx"
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: "=b"(new_flags));
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cpu.set_flags_oc(new_flags);
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return result;
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}
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DEFINE_GENERIC_SHIFT_ROTATE_INSN_HANDLERS(ROR, op_ror)
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void SoftCPU::SAHF(const X86::Instruction&) { TODO(); }
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void SoftCPU::SALC(const X86::Instruction&)
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