mirror of
https://github.com/RGBCube/serenity
synced 2025-07-25 15:07:45 +00:00
Kernel/PCI: Cache interrupt line and interrupt pin of a device
This allows us to remove the PCI::get_interrupt_line API function. As a result, this removes a bunch of not so great patterns that we used to cache PCI interrupt line in many IRQHandler derived classes instead of just using interrupt_number method of IRQHandler class.
This commit is contained in:
parent
057f5a12c2
commit
a411a44fda
17 changed files with 43 additions and 39 deletions
|
@ -17,7 +17,7 @@ namespace Kernel {
|
|||
|
||||
NonnullRefPtr<AHCIController> AHCIController::initialize(PCI::DeviceIdentifier const& pci_device_identifier)
|
||||
{
|
||||
return adopt_ref(*new AHCIController(pci_device_identifier.address()));
|
||||
return adopt_ref(*new AHCIController(pci_device_identifier));
|
||||
}
|
||||
|
||||
bool AHCIController::reset()
|
||||
|
@ -79,13 +79,13 @@ volatile AHCI::HBA& AHCIController::hba() const
|
|||
return static_cast<volatile AHCI::HBA&>(*(volatile AHCI::HBA*)(m_hba_region->vaddr().as_ptr()));
|
||||
}
|
||||
|
||||
AHCIController::AHCIController(PCI::Address address)
|
||||
AHCIController::AHCIController(PCI::DeviceIdentifier const& pci_device_identifier)
|
||||
: StorageController()
|
||||
, PCI::Device(address)
|
||||
, PCI::Device(pci_device_identifier.address())
|
||||
, m_hba_region(default_hba_region())
|
||||
, m_capabilities(capabilities())
|
||||
{
|
||||
initialize();
|
||||
initialize_hba(pci_device_identifier);
|
||||
}
|
||||
|
||||
AHCI::HBADefinedCapabilities AHCIController::capabilities() const
|
||||
|
@ -134,7 +134,7 @@ AHCIController::~AHCIController()
|
|||
{
|
||||
}
|
||||
|
||||
void AHCIController::initialize()
|
||||
void AHCIController::initialize_hba(PCI::DeviceIdentifier const& pci_device_identifier)
|
||||
{
|
||||
if (!reset()) {
|
||||
dmesgln("{}: AHCI controller reset failed", pci_address());
|
||||
|
@ -150,7 +150,7 @@ void AHCIController::initialize()
|
|||
PCI::enable_interrupt_line(pci_address());
|
||||
PCI::enable_bus_mastering(pci_address());
|
||||
enable_global_interrupts();
|
||||
m_handlers.append(AHCIPortHandler::create(*this, PCI::get_interrupt_line(pci_address()),
|
||||
m_handlers.append(AHCIPortHandler::create(*this, pci_device_identifier.interrupt_line().value(),
|
||||
AHCI::MaskedBitField((volatile u32&)(hba().control_regs.pi))));
|
||||
}
|
||||
|
||||
|
|
|
@ -41,8 +41,8 @@ private:
|
|||
void disable_global_interrupts() const;
|
||||
void enable_global_interrupts() const;
|
||||
|
||||
UNMAP_AFTER_INIT explicit AHCIController(PCI::Address address);
|
||||
UNMAP_AFTER_INIT void initialize();
|
||||
UNMAP_AFTER_INIT explicit AHCIController(PCI::DeviceIdentifier const&);
|
||||
UNMAP_AFTER_INIT void initialize_hba(PCI::DeviceIdentifier const&);
|
||||
|
||||
AHCI::HBADefinedCapabilities capabilities() const;
|
||||
RefPtr<StorageDevice> device_by_port(u32 index) const;
|
||||
|
|
|
@ -55,6 +55,7 @@ UNMAP_AFTER_INIT IDEController::IDEController(PCI::DeviceIdentifier const& devic
|
|||
: StorageController()
|
||||
, PCI::Device(device_identifier.address())
|
||||
, m_prog_if(device_identifier.prog_if())
|
||||
, m_interrupt_line(device_identifier.interrupt_line())
|
||||
{
|
||||
PCI::enable_io_space(device_identifier.address());
|
||||
PCI::enable_memory_space(device_identifier.address());
|
||||
|
@ -114,7 +115,7 @@ UNMAP_AFTER_INIT void IDEController::initialize(bool force_pio)
|
|||
{
|
||||
auto bus_master_base = IOAddress(PCI::get_BAR4(pci_address()) & (~1));
|
||||
dbgln("IDE controller @ {}: bus master base was set to {}", pci_address(), bus_master_base);
|
||||
dbgln("IDE controller @ {}: interrupt line was set to {}", pci_address(), PCI::get_interrupt_line(pci_address()));
|
||||
dbgln("IDE controller @ {}: interrupt line was set to {}", pci_address(), m_interrupt_line.value());
|
||||
dbgln("IDE controller @ {}: {}", pci_address(), detect_controller_type(m_prog_if.value()));
|
||||
dbgln("IDE controller @ {}: primary channel DMA capable? {}", pci_address(), ((bus_master_base.offset(2).in<u8>() >> 5) & 0b11));
|
||||
dbgln("IDE controller @ {}: secondary channel DMA capable? {}", pci_address(), ((bus_master_base.offset(2 + 8).in<u8>() >> 5) & 0b11));
|
||||
|
@ -131,7 +132,7 @@ UNMAP_AFTER_INIT void IDEController::initialize(bool force_pio)
|
|||
auto bar3 = PCI::get_BAR3(pci_address());
|
||||
auto secondary_control_io = (bar3 == 0x1 || bar3 == 0) ? IOAddress(0x376) : IOAddress(bar3 & (~1));
|
||||
|
||||
auto irq_line = PCI::get_interrupt_line(pci_address());
|
||||
auto irq_line = m_interrupt_line.value();
|
||||
if (is_pci_native_mode_enabled()) {
|
||||
VERIFY(irq_line != 0);
|
||||
}
|
||||
|
|
|
@ -46,5 +46,6 @@ private:
|
|||
NonnullRefPtrVector<IDEChannel> m_channels;
|
||||
// FIXME: Find a better way to get the ProgrammingInterface
|
||||
PCI::ProgrammingInterface m_prog_if;
|
||||
PCI::InterruptLine m_interrupt_line;
|
||||
};
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue