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https://github.com/RGBCube/serenity
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LibX86+UserspaceEmulator: Introduce AddressSize and OperandSize enums
These replace the bools a32 and o32, which will make implementing 64-bit sizes possible. :^)
This commit is contained in:
Simon Wanner
Andreas Kling
parent
7cd43deb28
commit
a7268c3c74
6 changed files with 276 additions and 152 deletions
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@ -258,9 +258,9 @@ void SoftCPU::do_once_or_repeat(const X86::Instruction& insn, Callback callback)
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if (!insn.has_rep_prefix())
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return callback();
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while (loop_index(insn.a32()).value()) {
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while (loop_index(insn.address_size()).value()) {
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callback();
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decrement_loop_index(insn.a32());
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decrement_loop_index(insn.address_size());
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if constexpr (check_zf) {
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warn_if_flags_tainted("repz/repnz");
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if (insn.rep_prefix() == X86::Prefix::REPZ && !zf())
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@ -1259,11 +1259,11 @@ ALWAYS_INLINE static void do_cmps(SoftCPU& cpu, const X86::Instruction& insn)
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{
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auto src_segment = cpu.segment(insn.segment_prefix().value_or(X86::SegmentRegister::DS));
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cpu.do_once_or_repeat<true>(insn, [&] {
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auto src = cpu.read_memory<T>({ src_segment, cpu.source_index(insn.a32()).value() });
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auto dest = cpu.read_memory<T>({ cpu.es(), cpu.destination_index(insn.a32()).value() });
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auto src = cpu.read_memory<T>({ src_segment, cpu.source_index(insn.address_size()).value() });
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auto dest = cpu.read_memory<T>({ cpu.es(), cpu.destination_index(insn.address_size()).value() });
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op_sub(cpu, dest, src);
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cpu.step_source_index(insn.a32(), sizeof(T));
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cpu.step_destination_index(insn.a32(), sizeof(T));
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cpu.step_source_index(insn.address_size(), sizeof(T));
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cpu.step_destination_index(insn.address_size(), sizeof(T));
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});
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}
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@ -1771,14 +1771,19 @@ void SoftCPU::IRET(const X86::Instruction&) { TODO_INSN(); }
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void SoftCPU::JCXZ_imm8(const X86::Instruction& insn)
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{
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if (insn.a32()) {
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switch (insn.address_size()) {
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case X86::AddressSize::Size32:
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warn_if_uninitialized(ecx(), "jecxz imm8");
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if (ecx().value() == 0)
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set_eip(eip() + (i8)insn.imm8());
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} else {
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break;
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case X86::AddressSize::Size16:
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warn_if_uninitialized(cx(), "jcxz imm8");
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if (cx().value() == 0)
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set_eip(eip() + (i8)insn.imm8());
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break;
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default:
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VERIFY_NOT_REACHED();
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}
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}
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@ -1865,9 +1870,9 @@ ALWAYS_INLINE static void do_lods(SoftCPU& cpu, const X86::Instruction& insn)
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{
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auto src_segment = cpu.segment(insn.segment_prefix().value_or(X86::SegmentRegister::DS));
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cpu.do_once_or_repeat<true>(insn, [&] {
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auto src = cpu.read_memory<T>({ src_segment, cpu.source_index(insn.a32()).value() });
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auto src = cpu.read_memory<T>({ src_segment, cpu.source_index(insn.address_size()).value() });
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cpu.gpr<T>(X86::RegisterAL) = src;
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cpu.step_source_index(insn.a32(), sizeof(T));
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cpu.step_source_index(insn.address_size(), sizeof(T));
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});
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}
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@ -1889,40 +1894,55 @@ void SoftCPU::LODSW(const X86::Instruction& insn)
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void SoftCPU::LOOPNZ_imm8(const X86::Instruction& insn)
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{
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warn_if_flags_tainted("loopnz");
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if (insn.a32()) {
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switch (insn.address_size()) {
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case X86::AddressSize::Size32:
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set_ecx({ ecx().value() - 1, ecx().shadow() });
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if (ecx().value() != 0 && !zf())
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set_eip(eip() + (i8)insn.imm8());
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} else {
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break;
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case X86::AddressSize::Size16:
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set_cx({ (u16)(cx().value() - 1), cx().shadow() });
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if (cx().value() != 0 && !zf())
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set_eip(eip() + (i8)insn.imm8());
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break;
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default:
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VERIFY_NOT_REACHED();
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}
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}
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void SoftCPU::LOOPZ_imm8(const X86::Instruction& insn)
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{
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warn_if_flags_tainted("loopz");
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if (insn.a32()) {
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switch (insn.address_size()) {
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case X86::AddressSize::Size32:
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set_ecx({ ecx().value() - 1, ecx().shadow() });
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if (ecx().value() != 0 && zf())
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set_eip(eip() + (i8)insn.imm8());
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} else {
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break;
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case X86::AddressSize::Size16:
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set_cx({ (u16)(cx().value() - 1), cx().shadow() });
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if (cx().value() != 0 && zf())
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set_eip(eip() + (i8)insn.imm8());
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break;
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default:
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VERIFY_NOT_REACHED();
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}
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}
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void SoftCPU::LOOP_imm8(const X86::Instruction& insn)
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{
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if (insn.a32()) {
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switch (insn.address_size()) {
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case X86::AddressSize::Size32:
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set_ecx({ ecx().value() - 1, ecx().shadow() });
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if (ecx().value() != 0)
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set_eip(eip() + (i8)insn.imm8());
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} else {
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break;
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case X86::AddressSize::Size16:
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set_cx({ (u16)(cx().value() - 1), cx().shadow() });
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if (cx().value() != 0)
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set_eip(eip() + (i8)insn.imm8());
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break;
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default:
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VERIFY_NOT_REACHED();
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}
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}
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@ -1937,10 +1957,10 @@ ALWAYS_INLINE static void do_movs(SoftCPU& cpu, const X86::Instruction& insn)
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{
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auto src_segment = cpu.segment(insn.segment_prefix().value_or(X86::SegmentRegister::DS));
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cpu.do_once_or_repeat<false>(insn, [&] {
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auto src = cpu.read_memory<T>({ src_segment, cpu.source_index(insn.a32()).value() });
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cpu.write_memory<T>({ cpu.es(), cpu.destination_index(insn.a32()).value() }, src);
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cpu.step_source_index(insn.a32(), sizeof(T));
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cpu.step_destination_index(insn.a32(), sizeof(T));
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auto src = cpu.read_memory<T>({ src_segment, cpu.source_index(insn.address_size()).value() });
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cpu.write_memory<T>({ cpu.es(), cpu.destination_index(insn.address_size()).value() }, src);
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cpu.step_source_index(insn.address_size(), sizeof(T));
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cpu.step_destination_index(insn.address_size(), sizeof(T));
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});
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}
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@ -2638,9 +2658,9 @@ ALWAYS_INLINE static void do_scas(SoftCPU& cpu, const X86::Instruction& insn)
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{
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cpu.do_once_or_repeat<true>(insn, [&] {
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auto src = cpu.const_gpr<T>(X86::RegisterAL);
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auto dest = cpu.read_memory<T>({ cpu.es(), cpu.destination_index(insn.a32()).value() });
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auto dest = cpu.read_memory<T>({ cpu.es(), cpu.destination_index(insn.address_size()).value() });
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op_sub(cpu, dest, src);
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cpu.step_destination_index(insn.a32(), sizeof(T));
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cpu.step_destination_index(insn.address_size(), sizeof(T));
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});
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}
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@ -2731,23 +2751,28 @@ void SoftCPU::STOSB(const X86::Instruction& insn)
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{
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if (insn.has_rep_prefix() && !df()) {
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// Fast path for 8-bit forward memory fill.
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if (m_emulator.mmu().fast_fill_memory8({ es(), destination_index(insn.a32()).value() }, ecx().value(), al())) {
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if (insn.a32()) {
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if (m_emulator.mmu().fast_fill_memory8({ es(), destination_index(insn.address_size()).value() }, ecx().value(), al())) {
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switch (insn.address_size()) {
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case X86::AddressSize::Size32:
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// FIXME: Should an uninitialized ECX taint EDI here?
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set_edi({ (u32)(edi().value() + ecx().value()), edi().shadow() });
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set_ecx(shadow_wrap_as_initialized<u32>(0));
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} else {
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break;
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case X86::AddressSize::Size16:
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// FIXME: Should an uninitialized CX taint DI here?
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set_di({ (u16)(di().value() + cx().value()), di().shadow() });
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set_cx(shadow_wrap_as_initialized<u16>(0));
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break;
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default:
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VERIFY_NOT_REACHED();
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}
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return;
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}
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}
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do_once_or_repeat<false>(insn, [&] {
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write_memory8({ es(), destination_index(insn.a32()).value() }, al());
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step_destination_index(insn.a32(), 1);
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write_memory8({ es(), destination_index(insn.address_size()).value() }, al());
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step_destination_index(insn.address_size(), 1);
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});
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}
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@ -2755,31 +2780,36 @@ void SoftCPU::STOSD(const X86::Instruction& insn)
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{
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if (insn.has_rep_prefix() && !df()) {
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// Fast path for 32-bit forward memory fill.
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if (m_emulator.mmu().fast_fill_memory32({ es(), destination_index(insn.a32()).value() }, ecx().value(), eax())) {
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if (insn.a32()) {
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if (m_emulator.mmu().fast_fill_memory32({ es(), destination_index(insn.address_size()).value() }, ecx().value(), eax())) {
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switch (insn.address_size()) {
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case X86::AddressSize::Size32:
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// FIXME: Should an uninitialized ECX taint EDI here?
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set_edi({ (u32)(edi().value() + (ecx().value() * sizeof(u32))), edi().shadow() });
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set_ecx(shadow_wrap_as_initialized<u32>(0));
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} else {
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break;
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case X86::AddressSize::Size16:
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// FIXME: Should an uninitialized CX taint DI here?
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set_di({ (u16)(di().value() + (cx().value() * sizeof(u32))), di().shadow() });
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set_cx(shadow_wrap_as_initialized<u16>(0));
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break;
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default:
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VERIFY_NOT_REACHED();
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}
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return;
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}
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}
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do_once_or_repeat<false>(insn, [&] {
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write_memory32({ es(), destination_index(insn.a32()).value() }, eax());
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step_destination_index(insn.a32(), 4);
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write_memory32({ es(), destination_index(insn.address_size()).value() }, eax());
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step_destination_index(insn.address_size(), 4);
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});
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}
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void SoftCPU::STOSW(const X86::Instruction& insn)
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{
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do_once_or_repeat<false>(insn, [&] {
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write_memory16({ es(), destination_index(insn.a32()).value() }, ax());
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step_destination_index(insn.a32(), 2);
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write_memory16({ es(), destination_index(insn.address_size()).value() }, ax());
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step_destination_index(insn.address_size(), 2);
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});
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}
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@ -2856,12 +2886,20 @@ void SoftCPU::XCHG_reg8_RM8(const X86::Instruction& insn)
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void SoftCPU::XLAT(const X86::Instruction& insn)
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{
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if (insn.a32())
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u32 offset;
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switch (insn.address_size()) {
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case X86::AddressSize::Size32:
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warn_if_uninitialized(ebx(), "xlat ebx");
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else
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offset = ebx().value() + al().value();
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break;
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case X86::AddressSize::Size16:
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warn_if_uninitialized(bx(), "xlat bx");
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offset = bx().value() + al().value();
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break;
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default:
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VERIFY_NOT_REACHED();
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}
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warn_if_uninitialized(al(), "xlat al");
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u32 offset = (insn.a32() ? ebx().value() : bx().value()) + al().value();
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set_al(read_memory8({ segment(insn.segment_prefix().value_or(X86::SegmentRegister::DS)), offset }));
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}
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