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https://github.com/RGBCube/serenity
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LibX86+UserspaceEmulator: Introduce AddressSize and OperandSize enums
These replace the bools a32 and o32, which will make implementing 64-bit sizes possible. :^)
This commit is contained in:
Simon Wanner
Andreas Kling
parent
7cd43deb28
commit
a7268c3c74
6 changed files with 276 additions and 152 deletions
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@ -42,6 +42,16 @@ constexpr T sign_extended_to(U value)
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return (TypeTrivia<T>::mask & ~TypeTrivia<U>::mask) | value;
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}
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enum class OperandSize : u8 {
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Size16,
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Size32,
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};
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enum class AddressSize : u8 {
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Size16,
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Size32,
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};
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enum IsLockPrefixAllowed {
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LockPrefixNotAllowed = 0,
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LockPrefixAllowed
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@ -214,27 +224,39 @@ struct InstructionDescriptor {
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// a non-null slashes member that's indexed by the three R/M bits.
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InstructionDescriptor* slashes { nullptr };
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unsigned imm1_bytes_for_address_size(bool a32) const
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unsigned imm1_bytes_for_address_size(AddressSize size) const
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{
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if (imm1_bytes == CurrentAddressSize)
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return a32 ? 4 : 2;
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if (imm1_bytes == CurrentAddressSize) {
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switch (size) {
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case AddressSize::Size32:
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return 4;
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case AddressSize::Size16:
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return 2;
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}
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VERIFY_NOT_REACHED();
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}
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return imm1_bytes;
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}
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unsigned imm2_bytes_for_address_size(bool a32) const
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unsigned imm2_bytes_for_address_size(AddressSize size) const
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{
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if (imm2_bytes == CurrentAddressSize)
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return a32 ? 4 : 2;
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if (imm2_bytes == CurrentAddressSize) {
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switch (size) {
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case AddressSize::Size32:
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return 4;
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case AddressSize::Size16:
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return 2;
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}
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VERIFY_NOT_REACHED();
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}
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return imm2_bytes;
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}
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IsLockPrefixAllowed lock_prefix_allowed { LockPrefixNotAllowed };
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};
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extern InstructionDescriptor s_table16[256];
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extern InstructionDescriptor s_table32[256];
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extern InstructionDescriptor s_0f_table16[256];
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extern InstructionDescriptor s_0f_table32[256];
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extern InstructionDescriptor s_table[2][256];
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extern InstructionDescriptor s_0f_table[2][256];
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extern InstructionDescriptor s_sse_table_np[256];
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extern InstructionDescriptor s_sse_table_66[256];
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extern InstructionDescriptor s_sse_table_f3[256];
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@ -469,7 +491,7 @@ private:
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String to_string_a32() const;
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template<typename InstructionStreamType>
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void decode(InstructionStreamType&, bool a32);
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void decode(InstructionStreamType&, AddressSize);
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template<typename InstructionStreamType>
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void decode16(InstructionStreamType&);
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template<typename InstructionStreamType>
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@ -497,7 +519,7 @@ private:
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class Instruction {
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public:
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template<typename InstructionStreamType>
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static Instruction from_stream(InstructionStreamType&, bool o32, bool a32);
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static Instruction from_stream(InstructionStreamType&, OperandSize, AddressSize);
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~Instruction() = default;
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ALWAYS_INLINE MemoryOrRegisterReference& modrm() const { return m_modrm; }
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@ -537,7 +559,16 @@ public:
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u16 imm16_2() const { return m_imm2; }
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u32 imm32_1() const { return imm32(); }
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u32 imm32_2() const { return m_imm2; }
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u32 imm_address() const { return m_a32 ? imm32() : imm16(); }
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u32 imm_address() const
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{
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switch (m_address_size) {
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case AddressSize::Size32:
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return imm32();
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case AddressSize::Size16:
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return imm16();
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}
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VERIFY_NOT_REACHED();
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}
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LogicalAddress imm_address16_16() const { return LogicalAddress(imm16_1(), imm16_2()); }
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LogicalAddress imm_address16_32() const { return LogicalAddress(imm16_1(), imm32_2()); }
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@ -556,13 +587,13 @@ public:
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u8 cc() const { return has_sub_op() ? m_sub_op & 0xf : m_op & 0xf; }
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bool a32() const { return m_a32; }
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AddressSize address_size() const { return m_address_size; }
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String to_string(u32 origin, SymbolProvider const* = nullptr, bool x32 = true) const;
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private:
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template<typename InstructionStreamType>
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Instruction(InstructionStreamType&, bool o32, bool a32);
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Instruction(InstructionStreamType&, OperandSize, AddressSize);
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void to_string_internal(StringBuilder&, u32 origin, SymbolProvider const*, bool x32) const;
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@ -580,8 +611,8 @@ private:
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u8 m_sub_op { 0 };
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u8 m_extra_bytes { 0 };
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u8 m_rep_prefix { 0 };
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bool m_a32 : 1 { false };
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bool m_o32 : 1 { false };
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OperandSize m_operand_size { OperandSize::Size16 };
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AddressSize m_address_size { AddressSize::Size16 };
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bool m_has_lock_prefix : 1 { false };
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bool m_has_operand_size_override_prefix : 1 { false };
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bool m_has_address_size_override_prefix : 1 { false };
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@ -819,9 +850,9 @@ ALWAYS_INLINE typename CPU::ValueWithShadowType256 MemoryOrRegisterReference::re
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}
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template<typename InstructionStreamType>
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ALWAYS_INLINE Instruction Instruction::from_stream(InstructionStreamType& stream, bool o32, bool a32)
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ALWAYS_INLINE Instruction Instruction::from_stream(InstructionStreamType& stream, OperandSize operand_size, AddressSize address_size)
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{
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return Instruction(stream, o32, a32);
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return Instruction(stream, operand_size, address_size);
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}
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ALWAYS_INLINE unsigned Instruction::length() const
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@ -860,20 +891,26 @@ ALWAYS_INLINE Optional<SegmentRegister> to_segment_prefix(u8 op)
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}
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template<typename InstructionStreamType>
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ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32, bool a32)
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: m_a32(a32)
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, m_o32(o32)
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ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, OperandSize operand_size, AddressSize address_size)
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: m_operand_size(operand_size)
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, m_address_size(address_size)
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{
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u8 prefix_bytes = 0;
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for (;; ++prefix_bytes) {
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u8 opbyte = stream.read8();
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if (opbyte == Prefix::OperandSizeOverride) {
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m_o32 = !o32;
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if (operand_size == OperandSize::Size32)
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m_operand_size = OperandSize::Size16;
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else if (operand_size == OperandSize::Size16)
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m_operand_size = OperandSize::Size32;
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m_has_operand_size_override_prefix = true;
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continue;
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}
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if (opbyte == Prefix::AddressSizeOverride) {
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m_a32 = !a32;
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if (address_size == AddressSize::Size32)
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m_address_size = AddressSize::Size16;
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else if (address_size == AddressSize::Size16)
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m_address_size = AddressSize::Size32;
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m_has_address_size_override_prefix = true;
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continue;
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}
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@ -896,9 +933,9 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
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if (m_op == 0x0f) {
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m_sub_op = stream.read8();
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m_descriptor = m_o32 ? &s_0f_table32[m_sub_op] : &s_0f_table16[m_sub_op];
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m_descriptor = &s_0f_table[to_underlying(m_operand_size)][m_sub_op];
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} else {
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m_descriptor = m_o32 ? &s_table32[m_op] : &s_table16[m_op];
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m_descriptor = &s_table[to_underlying(m_operand_size)][m_op];
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}
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if (m_descriptor->format == __SSE) {
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@ -906,7 +943,7 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
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m_descriptor = &s_sse_table_f3[m_sub_op];
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} else if (m_has_operand_size_override_prefix) {
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// This was unset while parsing the prefix initially
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m_o32 = true;
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m_operand_size = OperandSize::Size32;
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m_descriptor = &s_sse_table_66[m_sub_op];
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} else {
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m_descriptor = &s_sse_table_np[m_sub_op];
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@ -915,7 +952,7 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
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if (m_descriptor->has_rm) {
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// Consume ModR/M (may include SIB and displacement.)
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m_modrm.decode(stream, m_a32);
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m_modrm.decode(stream, m_address_size);
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m_register_index = m_modrm.reg();
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} else {
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if (has_sub_op())
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@ -947,8 +984,8 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
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return;
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}
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auto imm1_bytes = m_descriptor->imm1_bytes_for_address_size(m_a32);
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auto imm2_bytes = m_descriptor->imm2_bytes_for_address_size(m_a32);
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auto imm1_bytes = m_descriptor->imm1_bytes_for_address_size(m_address_size);
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auto imm2_bytes = m_descriptor->imm2_bytes_for_address_size(m_address_size);
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// Consume immediates if present.
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switch (imm2_bytes) {
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@ -992,11 +1029,11 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
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}
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template<typename InstructionStreamType>
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ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stream, bool a32)
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ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stream, AddressSize address_size)
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{
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m_rm_byte = stream.read8();
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if (a32) {
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if (address_size == AddressSize::Size32) {
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decode32(stream);
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switch (m_displacement_bytes) {
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case 0:
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@ -1009,9 +1046,8 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stre
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break;
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default:
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VERIFY_NOT_REACHED();
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break;
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}
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} else {
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} else if (address_size == AddressSize::Size16) {
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decode16(stream);
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switch (m_displacement_bytes) {
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case 0:
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@ -1024,8 +1060,9 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stre
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break;
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default:
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VERIFY_NOT_REACHED();
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break;
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}
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} else {
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VERIFY_NOT_REACHED();
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}
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}
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@ -1095,9 +1132,13 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode32(InstructionStreamType& st
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template<typename CPU>
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ALWAYS_INLINE LogicalAddress MemoryOrRegisterReference::resolve(const CPU& cpu, Instruction const& insn)
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{
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if (insn.a32())
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switch (insn.address_size()) {
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case AddressSize::Size16:
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return resolve16(cpu, insn.segment_prefix());
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case AddressSize::Size32:
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return resolve32(cpu, insn.segment_prefix());
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return resolve16(cpu, insn.segment_prefix());
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}
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VERIFY_NOT_REACHED();
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}
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}
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