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https://github.com/RGBCube/serenity
synced 2025-07-25 03:27:44 +00:00
Kernel: Fix some flaws that caused crashes or hangs during boot
We need to halt the BSP briefly until all APs are ready for the first context switch, but we can't hold the same spinlock by all of them while doing so. So, while the APs are waiting on each other they need to release the scheduler lock, and then once signaled re-acquire it. Should solve some timing dependent hangs or crashes, most easily observed using qemu with kvm disabled.
This commit is contained in:
Tom
Andreas Kling
parent
5d9ea2c787
commit
b02d33bd63
4 changed files with 146 additions and 120 deletions
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@ -990,8 +990,6 @@ void Processor::initialize(u32 cpu)
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if (cpu >= s_processors->size())
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s_processors->resize(cpu + 1);
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(*s_processors)[cpu] = this;
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klog() << "CPU[" << cpu << "]: initialized Processor at " << VirtualAddress(FlatPtr(this));
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}
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}
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@ -1344,6 +1342,27 @@ void Processor::assume_context(Thread& thread, u32 flags)
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ASSERT_NOT_REACHED();
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}
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extern "C" void pre_init_finished(void)
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{
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ASSERT(g_scheduler_lock.own_lock());
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// The target flags will get restored upon leaving the trap
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u32 prev_flags = cpu_flags();
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g_scheduler_lock.unlock(prev_flags);
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// We because init_finished() will wait on the other APs, we need
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// to release the scheduler lock so that the other APs can also get
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// to this point
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}
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extern "C" void post_init_finished(void)
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{
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// We need to re-acquire the scheduler lock before a context switch
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// transfers control into the idle loop, which needs the lock held
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ASSERT(!g_scheduler_lock.own_lock());
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g_scheduler_lock.lock();
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}
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void Processor::initialize_context_switching(Thread& initial_thread)
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{
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ASSERT(initial_thread.process().is_ring0());
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@ -1368,9 +1387,11 @@ void Processor::initialize_context_switching(Thread& initial_thread)
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"addl $20, %%ebx \n" // calculate pointer to TrapFrame
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"pushl %%ebx \n"
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"cld \n"
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"pushl %[cpu] \n"
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"pushl %[cpu] \n" // push argument for init_finished before register is clobbered
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"call pre_init_finished \n"
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"call init_finished \n"
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"addl $4, %%esp \n"
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"call post_init_finished \n"
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"call enter_trap_no_irq \n"
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"addl $4, %%esp \n"
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"lret \n"
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@ -289,106 +289,109 @@ bool APIC::init_bsp()
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void APIC::do_boot_aps()
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{
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if (m_processor_enabled_cnt > 1) {
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u32 aps_to_enable = m_processor_enabled_cnt - 1;
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ASSERT(m_processor_enabled_cnt > 1);
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u32 aps_to_enable = m_processor_enabled_cnt - 1;
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// Copy the APIC startup code and variables to P0x00008000
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// Also account for the data appended to:
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// * aps_to_enable u32 values for ap_cpu_init_stacks
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// * aps_to_enable u32 values for ap_cpu_init_processor_info_array
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auto apic_startup_region = MM.allocate_kernel_region_identity(PhysicalAddress(0x8000), PAGE_ROUND_UP(apic_ap_start_size + (2 * aps_to_enable * sizeof(u32))), {}, Region::Access::Read | Region::Access::Write | Region::Access::Execute);
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memcpy(apic_startup_region->vaddr().as_ptr(), reinterpret_cast<const void*>(apic_ap_start), apic_ap_start_size);
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// Copy the APIC startup code and variables to P0x00008000
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// Also account for the data appended to:
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// * aps_to_enable u32 values for ap_cpu_init_stacks
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// * aps_to_enable u32 values for ap_cpu_init_processor_info_array
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auto apic_startup_region = MM.allocate_kernel_region_identity(PhysicalAddress(0x8000), PAGE_ROUND_UP(apic_ap_start_size + (2 * aps_to_enable * sizeof(u32))), {}, Region::Access::Read | Region::Access::Write | Region::Access::Execute);
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memcpy(apic_startup_region->vaddr().as_ptr(), reinterpret_cast<const void*>(apic_ap_start), apic_ap_start_size);
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// Allocate enough stacks for all APs
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for (u32 i = 0; i < aps_to_enable; i++) {
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auto stack_region = MM.allocate_kernel_region(Thread::default_kernel_stack_size, {}, Region::Access::Read | Region::Access::Write, false, true, true);
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if (!stack_region) {
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klog() << "APIC: Failed to allocate stack for AP #" << i;
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return;
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}
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stack_region->set_stack(true);
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m_apic_ap_stacks.append(move(stack_region));
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// Allocate enough stacks for all APs
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Vector<OwnPtr<Region>> apic_ap_stacks;
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for (u32 i = 0; i < aps_to_enable; i++) {
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auto stack_region = MM.allocate_kernel_region(Thread::default_kernel_stack_size, {}, Region::Access::Read | Region::Access::Write, false, true, true);
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if (!stack_region) {
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klog() << "APIC: Failed to allocate stack for AP #" << i;
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return;
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}
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stack_region->set_stack(true);
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apic_ap_stacks.append(move(stack_region));
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}
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// Store pointers to all stacks for the APs to use
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auto ap_stack_array = APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_stacks);
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ASSERT(aps_to_enable == m_apic_ap_stacks.size());
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for (size_t i = 0; i < aps_to_enable; i++) {
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ap_stack_array[i] = m_apic_ap_stacks[i]->vaddr().get() + Thread::default_kernel_stack_size;
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// Store pointers to all stacks for the APs to use
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auto ap_stack_array = APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_stacks);
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ASSERT(aps_to_enable == apic_ap_stacks.size());
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for (size_t i = 0; i < aps_to_enable; i++) {
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ap_stack_array[i] = apic_ap_stacks[i]->vaddr().get() + Thread::default_kernel_stack_size;
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#ifdef APIC_DEBUG
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klog() << "APIC: CPU[" << (i + 1) << "] stack at " << VirtualAddress(ap_stack_array[i]);
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#endif
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}
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// Allocate Processor structures for all APs and store the pointer to the data
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m_ap_processor_info.resize(aps_to_enable);
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for (size_t i = 0; i < aps_to_enable; i++)
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m_ap_processor_info[i] = make<Processor>();
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auto ap_processor_info_array = &ap_stack_array[aps_to_enable];
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for (size_t i = 0; i < aps_to_enable; i++) {
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ap_processor_info_array[i] = FlatPtr(m_ap_processor_info[i].ptr());
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#ifdef APIC_DEBUG
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klog() << "APIC: CPU[" << (i + 1) << "] Processor at " << VirtualAddress(ap_processor_info_array[i]);
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#endif
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}
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_processor_info_array) = FlatPtr(&ap_processor_info_array[0]);
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// Store the BSP's CR3 value for the APs to use
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_cr3) = MM.kernel_page_directory().cr3();
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// Store the BSP's GDT and IDT for the APs to use
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const auto& gdtr = Processor::current().get_gdtr();
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_gdtr) = FlatPtr(&gdtr);
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const auto& idtr = get_idtr();
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_idtr) = FlatPtr(&idtr);
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// Store the BSP's CR0 and CR4 values for the APs to use
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_cr0) = read_cr0();
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_cr4) = read_cr4();
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// Create an idle thread for each processor. We have to do this here
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// because we won't be able to send FlushTLB messages, so we have to
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// have all memory set up for the threads so that when the APs are
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// starting up, they can access all the memory properly
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m_ap_idle_threads.resize(aps_to_enable);
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for (u32 i = 0; i < aps_to_enable; i++)
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m_ap_idle_threads[i] = Scheduler::create_ap_idle_thread(i + 1);
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#ifdef APIC_DEBUG
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klog() << "APIC: Starting " << aps_to_enable << " AP(s)";
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#endif
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// INIT
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write_icr(ICRReg(0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
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IO::delay(10 * 1000);
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for (int i = 0; i < 2; i++) {
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// SIPI
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write_icr(ICRReg(0x08, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf)); // start execution at P8000
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IO::delay(200);
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}
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// Now wait until the ap_cpu_init_pending variable dropped to 0, which means all APs are initialized and no longer need these special mappings
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if (m_apic_ap_count.load(AK::MemoryOrder::memory_order_consume) != aps_to_enable) {
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#ifdef APIC_DEBUG
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klog() << "APIC: Waiting for " << aps_to_enable << " AP(s) to finish initialization...";
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#endif
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do {
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// Wait a little bit
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IO::delay(200);
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} while (m_apic_ap_count.load(AK::MemoryOrder::memory_order_consume) != aps_to_enable);
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}
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#ifdef APIC_DEBUG
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klog() << "APIC: " << m_processor_enabled_cnt << " processors are initialized and running";
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klog() << "APIC: CPU[" << (i + 1) << "] stack at " << VirtualAddress(ap_stack_array[i]);
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#endif
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}
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// Allocate Processor structures for all APs and store the pointer to the data
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m_ap_processor_info.resize(aps_to_enable);
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for (size_t i = 0; i < aps_to_enable; i++)
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m_ap_processor_info[i] = make<Processor>();
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auto ap_processor_info_array = &ap_stack_array[aps_to_enable];
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for (size_t i = 0; i < aps_to_enable; i++) {
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ap_processor_info_array[i] = FlatPtr(m_ap_processor_info[i].ptr());
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#ifdef APIC_DEBUG
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klog() << "APIC: CPU[" << (i + 1) << "] Processor at " << VirtualAddress(ap_processor_info_array[i]);
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#endif
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}
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_processor_info_array) = FlatPtr(&ap_processor_info_array[0]);
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// Store the BSP's CR3 value for the APs to use
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_cr3) = MM.kernel_page_directory().cr3();
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// Store the BSP's GDT and IDT for the APs to use
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const auto& gdtr = Processor::current().get_gdtr();
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_gdtr) = FlatPtr(&gdtr);
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const auto& idtr = get_idtr();
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_idtr) = FlatPtr(&idtr);
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// Store the BSP's CR0 and CR4 values for the APs to use
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_cr0) = read_cr0();
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*APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_cr4) = read_cr4();
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// Create an idle thread for each processor. We have to do this here
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// because we won't be able to send FlushTLB messages, so we have to
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// have all memory set up for the threads so that when the APs are
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// starting up, they can access all the memory properly
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m_ap_idle_threads.resize(aps_to_enable);
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for (u32 i = 0; i < aps_to_enable; i++)
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m_ap_idle_threads[i] = Scheduler::create_ap_idle_thread(i + 1);
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#ifdef APIC_DEBUG
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klog() << "APIC: Starting " << aps_to_enable << " AP(s)";
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#endif
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// INIT
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write_icr(ICRReg(0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
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IO::delay(10 * 1000);
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for (int i = 0; i < 2; i++) {
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// SIPI
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write_icr(ICRReg(0x08, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf)); // start execution at P8000
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IO::delay(200);
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}
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// Now wait until the ap_cpu_init_pending variable dropped to 0, which means all APs are initialized and no longer need these special mappings
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if (m_apic_ap_count.load(AK::MemoryOrder::memory_order_consume) != aps_to_enable) {
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#ifdef APIC_DEBUG
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klog() << "APIC: Waiting for " << aps_to_enable << " AP(s) to finish initialization...";
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#endif
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do {
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// Wait a little bit
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IO::delay(200);
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} while (m_apic_ap_count.load(AK::MemoryOrder::memory_order_consume) != aps_to_enable);
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}
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#ifdef APIC_DEBUG
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klog() << "APIC: " << m_processor_enabled_cnt << " processors are initialized and running";
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#endif
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}
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void APIC::boot_aps()
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{
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if (m_processor_enabled_cnt <= 1)
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return;
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// We split this into another call because do_boot_aps() will cause
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// MM calls upon exit, and we don't want to call smp_enable before that
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do_boot_aps();
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@ -396,10 +399,13 @@ void APIC::boot_aps()
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// Enable SMP, which means IPIs may now be sent
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Processor::smp_enable();
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#ifdef APIC_DEBUG
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dbg() << "All processors initialized and waiting, trigger all to continue";
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#endif
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// Now trigger all APs to continue execution (need to do this after
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// the regions have been freed so that we don't trigger IPIs
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if (m_processor_enabled_cnt > 1)
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m_apic_ap_continue.store(1, AK::MemoryOrder::memory_order_release);
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m_apic_ap_continue.store(1, AK::MemoryOrder::memory_order_release);
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}
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void APIC::enable(u32 cpu)
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@ -446,23 +452,6 @@ void APIC::enable(u32 cpu)
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write_register(APIC_REG_LVT_LINT1, APIC_LVT(0, 0) | APIC_LVT_TRIGGER_LEVEL);
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write_register(APIC_REG_TPR, 0);
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if (cpu > 0) {
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// Notify the BSP that we are done initializing. It will unmap the startup data at P8000
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m_apic_ap_count.fetch_add(1, AK::MemoryOrder::memory_order_acq_rel);
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#ifdef APIC_DEBUG
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klog() << "APIC: cpu #" << cpu << " initialized, waiting for all others";
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#endif
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// The reason we're making all APs wait until the BSP signals them is that
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// we don't want APs to trigger IPIs (e.g. through MM) while the BSP
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// is unable to process them
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while (!m_apic_ap_continue.load(AK::MemoryOrder::memory_order_consume)) {
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IO::delay(200);
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}
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// boot_aps() freed memory, so we need to update our tlb
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Processor::flush_entire_tlb_local();
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}
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}
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Thread* APIC::get_idle_thread(u32 cpu) const
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@ -475,12 +464,33 @@ void APIC::init_finished(u32 cpu)
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{
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// This method is called once the boot stack is no longer needed
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ASSERT(cpu > 0);
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ASSERT(cpu <= m_apic_ap_count);
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ASSERT(m_apic_ap_stacks[cpu - 1]);
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ASSERT(cpu < m_processor_enabled_cnt);
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// Since we're waiting on other APs here, we shouldn't have the
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// scheduler lock
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ASSERT(!g_scheduler_lock.own_lock());
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// Notify the BSP that we are done initializing. It will unmap the startup data at P8000
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m_apic_ap_count.fetch_add(1, AK::MemoryOrder::memory_order_acq_rel);
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#ifdef APIC_DEBUG
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klog() << "APIC: boot stack for for cpu #" << cpu << " no longer needed";
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klog() << "APIC: cpu #" << cpu << " initialized, waiting for all others";
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#endif
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m_apic_ap_stacks[cpu - 1].clear();
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// The reason we're making all APs wait until the BSP signals them is that
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// we don't want APs to trigger IPIs (e.g. through MM) while the BSP
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// is unable to process them
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while (!m_apic_ap_continue.load(AK::MemoryOrder::memory_order_consume)) {
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IO::delay(200);
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}
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#ifdef APIC_DEBUG
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klog() << "APIC: cpu #" << cpu << " continues, all others are initialized";
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#endif
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// do_boot_aps() freed memory, so we need to update our tlb
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Processor::flush_entire_tlb_local();
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// Now enable all the interrupts
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APIC::the().enable(cpu);
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}
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void APIC::broadcast_ipi()
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@ -96,7 +96,6 @@ private:
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};
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OwnPtr<Region> m_apic_base;
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Vector<OwnPtr<Region>> m_apic_ap_stacks;
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Vector<OwnPtr<Processor>> m_ap_processor_info;
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Vector<Thread*> m_ap_idle_threads;
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AK::Atomic<u8> m_apic_ap_count{0};
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@ -166,10 +166,7 @@ extern "C" [[noreturn]] void init_ap(u32 cpu, Processor* processor_info)
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{
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processor_info->early_initialize(cpu);
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klog() << "CPU #" << cpu << " processor_info at " << VirtualAddress(FlatPtr(processor_info));
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processor_info->initialize(cpu);
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APIC::the().enable(cpu);
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MemoryManager::initialize(cpu);
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Scheduler::set_idle_thread(APIC::the().get_idle_thread(cpu));
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@ -184,7 +181,6 @@ extern "C" [[noreturn]] void init_ap(u32 cpu, Processor* processor_info)
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//
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extern "C" void init_finished(u32 cpu)
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{
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klog() << "CPU #" << cpu << " finished initialization";
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if (cpu == 0) {
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// TODO: we can reuse the boot stack, maybe for kmalloc()?
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} else {
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Add a link
Reference in a new issue