From b6ac2ed34d2437ffd77195772a0518a8954c1994 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?S=C3=B6nke=20Holz?= <sholz8530@gmail.com>
Date: Sun, 22 Oct 2023 11:17:53 +0200
Subject: [PATCH] Kernel/riscv64: Implement RISC-V SmapDisabler

---
 Kernel/Arch/riscv64/SmapDisabler.cpp | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Kernel/Arch/riscv64/SmapDisabler.cpp

diff --git a/Kernel/Arch/riscv64/SmapDisabler.cpp b/Kernel/Arch/riscv64/SmapDisabler.cpp
new file mode 100644
index 0000000000..324ca3ed95
--- /dev/null
+++ b/Kernel/Arch/riscv64/SmapDisabler.cpp
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023, Sönke Holz <sholz8530@gmail.com>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <Kernel/Arch/SmapDisabler.h>
+#include <Kernel/Arch/riscv64/CSR.h>
+
+namespace Kernel {
+
+SmapDisabler::SmapDisabler()
+    : m_flags(RISCV64::CSR::read_and_set_bits(RISCV64::CSR::Address::SSTATUS, 1 << to_underlying(RISCV64::CSR::SSTATUS::Offset::SUM)))
+{
+}
+
+SmapDisabler::~SmapDisabler()
+{
+    if ((m_flags & (1 << to_underlying(RISCV64::CSR::SSTATUS::Offset::SUM))) == 0)
+        RISCV64::CSR::clear_bits(RISCV64::CSR::Address::SSTATUS, 1 << to_underlying(RISCV64::CSR::SSTATUS::Offset::SUM));
+}
+
+}