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Kernel/Graphics: Move Intel graphics related code to a separate folder
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4 changed files with 3 additions and 3 deletions
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/*
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/String.h>
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#include <AK/Types.h>
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#include <Kernel/Bus/PCI/DeviceController.h>
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#include <Kernel/Graphics/Definitions.h>
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#include <Kernel/Graphics/FramebufferDevice.h>
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#include <Kernel/Graphics/VGACompatibleAdapter.h>
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#include <Kernel/PhysicalAddress.h>
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namespace Kernel {
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namespace IntelGraphics {
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enum RegisterIndex {
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PipeAConf = 0x70008,
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PipeBConf = 0x71008,
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GMBusData = 0x510C,
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GMBusStatus = 0x5108,
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GMBusCommand = 0x5104,
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GMBusClock = 0x5100,
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DisplayPlaneAControl = 0x70180,
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DisplayPlaneALinearOffset = 0x70184,
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DisplayPlaneAStride = 0x70188,
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DisplayPlaneASurface = 0x7019C,
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DPLLDivisorA0 = 0x6040,
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DPLLDivisorA1 = 0x6044,
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DPLLControlA = 0x6014,
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DPLLControlB = 0x6018,
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DPLLMultiplierA = 0x601C,
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HTotalA = 0x60000,
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HBlankA = 0x60004,
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HSyncA = 0x60008,
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VTotalA = 0x6000C,
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VBlankA = 0x60010,
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VSyncA = 0x60014,
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PipeASource = 0x6001C,
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AnalogDisplayPort = 0x61100,
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VGADisplayPlaneControl = 0x71400,
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};
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}
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class IntelNativeGraphicsAdapter final
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: public VGACompatibleAdapter {
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AK_MAKE_ETERNAL
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public:
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struct PLLSettings {
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bool is_valid() const { return (n != 0 && m1 != 0 && m2 != 0 && p1 != 0 && p2 != 0); }
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u64 compute_dot_clock(u64 refclock) const
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{
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return (refclock * (5 * (m1) + (m2)) / (n)) / (p1 * p2);
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}
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u64 compute_vco(u64 refclock) const
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{
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return refclock * (5 * (m1) + (m2)) / n;
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}
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u64 compute_m() const
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{
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return 5 * (m1) + (m2);
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}
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u64 compute_p() const
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{
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return p1 * p2;
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}
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u64 n { 0 };
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u64 m1 { 0 };
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u64 m2 { 0 };
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u64 p1 { 0 };
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u64 p2 { 0 };
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};
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struct PLLParameterLimit {
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size_t min, max;
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};
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struct PLLMaxSettings {
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PLLParameterLimit dot_clock, vco, n, m, m1, m2, p, p1, p2;
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};
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private:
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enum GMBusPinPair : u8 {
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None = 0,
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DedicatedControl = 1,
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DedicatedAnalog = 0b10,
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IntegratedDigital = 0b11,
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sDVO = 0b101,
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Dconnector = 0b111,
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};
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enum class GMBusStatus {
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TransactionCompletion,
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HardwareReady
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};
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enum GMBusCycle {
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Wait = 1,
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Stop = 4,
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};
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public:
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static RefPtr<IntelNativeGraphicsAdapter> initialize(PCI::Address);
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private:
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explicit IntelNativeGraphicsAdapter(PCI::Address);
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void write_to_register(IntelGraphics::RegisterIndex, u32 value) const;
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u32 read_from_register(IntelGraphics::RegisterIndex) const;
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// ^GraphicsDevice
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virtual void initialize_framebuffer_devices() override;
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virtual Type type() const override { return Type::VGACompatible; }
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bool pipe_a_enabled() const;
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bool pipe_b_enabled() const;
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bool is_resolution_valid(size_t width, size_t height);
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bool set_crt_resolution(size_t width, size_t height);
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void disable_output();
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void enable_output(PhysicalAddress fb_address, size_t width);
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void disable_vga_emulation();
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void enable_vga_plane();
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void disable_dac_output();
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void enable_dac_output();
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void disable_all_planes();
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void disable_pipe_a();
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void disable_pipe_b();
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void disable_dpll();
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void set_dpll_registers(const PLLSettings&);
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void enable_dpll_without_vga(const PLLSettings&, size_t dac_multiplier);
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void set_display_timings(const Graphics::Modesetting&);
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void enable_pipe_a();
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void set_framebuffer_parameters(size_t, size_t);
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void enable_primary_plane(PhysicalAddress fb_address, size_t stride);
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bool wait_for_enabled_pipe_a(size_t milliseconds_timeout) const;
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bool wait_for_disabled_pipe_a(size_t milliseconds_timeout) const;
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bool wait_for_disabled_pipe_b(size_t milliseconds_timeout) const;
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void set_gmbus_default_rate();
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void set_gmbus_pin_pair(GMBusPinPair pin_pair);
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// FIXME: It would be better if we generalize the I2C access later on
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void gmbus_read_edid();
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void gmbus_write(unsigned address, u32 byte);
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void gmbus_read(unsigned address, u8* buf, size_t length);
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bool gmbus_wait_for(GMBusStatus desired_status, Optional<size_t> milliseconds_timeout);
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Optional<PLLSettings> create_pll_settings(u64 target_frequency, u64 reference_clock, const PLLMaxSettings&);
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SpinLock<u8> m_control_lock;
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SpinLock<u8> m_modeset_lock;
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mutable SpinLock<u8> m_registers_lock;
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Graphics::VideoInfoBlock m_crt_edid;
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const PhysicalAddress m_registers;
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const PhysicalAddress m_framebuffer_addr;
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OwnPtr<Region> m_registers_region;
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};
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}
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