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https://github.com/RGBCube/serenity
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Kernel/aarch64: Add volatile modifier to various asm statements
This prevents the optimizer from reordering them, which hopefully prevents future bugs.
This commit is contained in:
parent
10030038e9
commit
baa5cb9e30
2 changed files with 76 additions and 76 deletions
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@ -16,36 +16,36 @@ namespace Kernel::Aarch64::Asm {
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inline void set_ttbr1_el1(FlatPtr ttbr1_el1)
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{
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asm("msr ttbr1_el1, %[value]" ::[value] "r"(ttbr1_el1));
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asm volatile("msr ttbr1_el1, %[value]" ::[value] "r"(ttbr1_el1));
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}
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inline void set_ttbr0_el1(FlatPtr ttbr0_el1)
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{
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asm("msr ttbr0_el1, %[value]" ::[value] "r"(ttbr0_el1));
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asm volatile("msr ttbr0_el1, %[value]" ::[value] "r"(ttbr0_el1));
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}
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inline FlatPtr get_ttbr0_el1()
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{
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FlatPtr ttbr0_el1;
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asm("mrs %[value], ttbr0_el1\n"
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: [value] "=r"(ttbr0_el1));
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asm volatile("mrs %[value], ttbr0_el1\n"
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: [value] "=r"(ttbr0_el1));
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return ttbr0_el1;
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}
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inline void set_sp_el1(FlatPtr sp_el1)
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{
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asm("msr sp_el1, %[value]" ::[value] "r"(sp_el1));
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asm volatile("msr sp_el1, %[value]" ::[value] "r"(sp_el1));
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}
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inline void set_tpidr_el0(FlatPtr tpidr_el0)
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{
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asm("msr tpidr_el0, %[value]" ::[value] "r"(tpidr_el0));
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asm volatile("msr tpidr_el0, %[value]" ::[value] "r"(tpidr_el0));
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}
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inline void flush()
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{
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asm("dsb ish");
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asm("isb");
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asm volatile("dsb ish");
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asm volatile("isb");
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}
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[[noreturn]] inline void halt()
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@ -66,8 +66,8 @@ inline ExceptionLevel get_current_exception_level()
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{
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u64 current_exception_level;
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asm("mrs %[value], CurrentEL"
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: [value] "=r"(current_exception_level));
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asm volatile("mrs %[value], CurrentEL"
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: [value] "=r"(current_exception_level));
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current_exception_level = (current_exception_level >> 2) & 0x3;
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return static_cast<ExceptionLevel>(current_exception_level);
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@ -83,7 +83,7 @@ inline void wait_cycles(int n)
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inline void load_el1_vector_table(void* vector_table)
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{
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asm("msr VBAR_EL1, %[value]" ::[value] "r"(vector_table));
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asm volatile("msr VBAR_EL1, %[value]" ::[value] "r"(vector_table));
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}
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inline void enter_el2_from_el3()
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@ -38,8 +38,8 @@ struct alignas(u64) ID_AA64ISAR0_EL1 {
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{
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ID_AA64ISAR0_EL1 feature_register;
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asm("mrs %[value], ID_AA64ISAR0_EL1"
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], ID_AA64ISAR0_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -70,8 +70,8 @@ struct alignas(u64) ID_AA64ISAR1_EL1 {
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{
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ID_AA64ISAR1_EL1 feature_register;
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asm("mrs %[value], ID_AA64ISAR1_EL1"
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], ID_AA64ISAR1_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -101,8 +101,8 @@ struct alignas(u64) ID_AA64ISAR2_EL1 {
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{
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ID_AA64ISAR2_EL1 feature_register;
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asm("mrs %[value], ID_AA64ISAR2_EL1"
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], ID_AA64ISAR2_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -133,8 +133,8 @@ struct alignas(u64) ID_AA64PFR0_EL1 {
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{
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ID_AA64PFR0_EL1 feature_register;
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asm("mrs %[value], ID_AA64PFR0_EL1"
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], ID_AA64PFR0_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -165,8 +165,8 @@ struct alignas(u64) ID_AA64PFR1_EL1 {
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{
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ID_AA64PFR1_EL1 feature_register;
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asm("mrs %[value], ID_AA64PFR1_EL1"
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], ID_AA64PFR1_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -186,8 +186,8 @@ struct alignas(u64) ID_AA64PFR2_EL1 {
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{
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ID_AA64PFR2_EL1 feature_register;
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asm("mrs %[value], s3_0_c0_c4_2" // encoded ID_AA64PFR2_EL1 register
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], s3_0_c0_c4_2" // encoded ID_AA64PFR2_EL1 register
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -211,8 +211,8 @@ struct alignas(u64) MPIDR_EL1 {
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{
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MPIDR_EL1 affinity_register;
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asm("mrs %[value], MPIDR_EL1"
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: [value] "=r"(affinity_register));
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asm volatile("mrs %[value], MPIDR_EL1"
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: [value] "=r"(affinity_register));
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return affinity_register;
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}
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@ -242,8 +242,8 @@ struct alignas(u64) ID_AA64MMFR0_EL1 {
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{
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ID_AA64MMFR0_EL1 feature_register;
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asm("mrs %[value], ID_AA64MMFR0_EL1"
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], ID_AA64MMFR0_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -274,8 +274,8 @@ struct alignas(u64) ID_AA64MMFR1_EL1 {
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{
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ID_AA64MMFR1_EL1 feature_register;
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asm("mrs %[value], ID_AA64MMFR1_EL1"
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], ID_AA64MMFR1_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -306,8 +306,8 @@ struct alignas(u64) ID_AA64MMFR2_EL1 {
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{
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ID_AA64MMFR2_EL1 feature_register;
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asm("mrs %[value], ID_AA64MMFR2_EL1"
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], ID_AA64MMFR2_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -338,8 +338,8 @@ struct alignas(u64) ID_AA64MMFR3_EL1 {
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{
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ID_AA64MMFR3_EL1 feature_register;
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asm("mrs %[value], s3_0_c0_c7_3" // encoded ID_AA64MMFR3_EL1 register
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], s3_0_c0_c7_3" // encoded ID_AA64MMFR3_EL1 register
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -358,8 +358,8 @@ struct alignas(u64) ID_AA64MMFR4_EL1 {
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{
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ID_AA64MMFR4_EL1 feature_register;
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asm("mrs %[value], s3_0_c0_c7_4" // encoded ID_AA64MMFR4_EL1 register
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], s3_0_c0_c7_4" // encoded ID_AA64MMFR4_EL1 register
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -390,8 +390,8 @@ struct alignas(u64) ID_AA64SMFR0_EL1 {
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{
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ID_AA64SMFR0_EL1 feature_register;
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asm("mrs %[value], s3_0_c0_c4_5" // encoded ID_AA64SMFR0_EL1 register
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], s3_0_c0_c4_5" // encoded ID_AA64SMFR0_EL1 register
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -421,8 +421,8 @@ struct alignas(u64) ID_AA64ZFR0_EL1 {
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{
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ID_AA64ZFR0_EL1 feature_register;
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asm("mrs %[value], s3_0_c0_c4_4" // encoded ID_AA64ZFR0_EL1 register
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], s3_0_c0_c4_4" // encoded ID_AA64ZFR0_EL1 register
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -453,8 +453,8 @@ struct alignas(u64) ID_AA64DFR0_EL1 {
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{
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ID_AA64DFR0_EL1 feature_register;
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asm("mrs %[value], ID_AA64DFR0_EL1"
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], ID_AA64DFR0_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -480,8 +480,8 @@ struct alignas(u64) ID_AA64DFR1_EL1 {
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{
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ID_AA64DFR1_EL1 feature_register;
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asm("mrs %[value], ID_AA64DFR1_EL1"
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: [value] "=r"(feature_register));
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asm volatile("mrs %[value], ID_AA64DFR1_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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@ -498,8 +498,8 @@ struct alignas(u64) CNTFRQ_EL0 {
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{
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CNTFRQ_EL0 frequency;
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asm("mrs %[value], CNTFRQ_EL0"
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: [value] "=r"(frequency));
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asm volatile("mrs %[value], CNTFRQ_EL0"
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: [value] "=r"(frequency));
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return frequency;
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}
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@ -597,15 +597,15 @@ struct alignas(u64) TCR_EL1 {
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static inline void write(TCR_EL1 tcr_el1)
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{
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asm("msr tcr_el1, %[value]" ::[value] "r"(tcr_el1));
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asm volatile("msr tcr_el1, %[value]" ::[value] "r"(tcr_el1));
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}
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static inline TCR_EL1 read()
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{
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TCR_EL1 tcr_el1;
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asm("mrs %[value], tcr_el1_el1"
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: [value] "=r"(tcr_el1));
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asm volatile("mrs %[value], tcr_el1"
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: [value] "=r"(tcr_el1));
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return tcr_el1;
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}
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@ -672,15 +672,15 @@ struct alignas(u64) SCTLR_EL1 {
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static inline void write(SCTLR_EL1 sctlr_el1)
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{
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asm("msr sctlr_el1, %[value]" ::[value] "r"(sctlr_el1));
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asm volatile("msr sctlr_el1, %[value]" ::[value] "r"(sctlr_el1));
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}
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static inline SCTLR_EL1 read()
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{
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SCTLR_EL1 sctlr;
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asm("mrs %[value], sctlr_el1"
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: [value] "=r"(sctlr));
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asm volatile("mrs %[value], sctlr_el1"
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: [value] "=r"(sctlr));
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return sctlr;
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}
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@ -711,8 +711,8 @@ struct alignas(u64) MIDR_EL1 {
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{
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MIDR_EL1 main_id_register;
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asm("mrs %[value], MIDR_EL1"
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: [value] "=r"(main_id_register));
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asm volatile("mrs %[value], MIDR_EL1"
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: [value] "=r"(main_id_register));
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return main_id_register;
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}
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@ -728,8 +728,8 @@ struct alignas(u64) AIDR_EL1 {
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{
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AIDR_EL1 auxiliary_id_register;
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asm("mrs %[value], AIDR_EL1"
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: [value] "=r"(auxiliary_id_register));
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asm volatile("mrs %[value], AIDR_EL1"
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: [value] "=r"(auxiliary_id_register));
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return auxiliary_id_register;
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}
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@ -786,15 +786,15 @@ struct alignas(u64) HCR_EL2 {
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static inline void write(HCR_EL2 hcr_el2)
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{
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asm("msr hcr_el2, %[value]" ::[value] "r"(hcr_el2));
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asm volatile("msr hcr_el2, %[value]" ::[value] "r"(hcr_el2));
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}
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static inline HCR_EL2 read()
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{
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HCR_EL2 spsr;
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asm("mrs %[value], hcr_el2"
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: [value] "=r"(spsr));
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asm volatile("mrs %[value], hcr_el2"
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: [value] "=r"(spsr));
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return spsr;
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}
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@ -842,15 +842,15 @@ struct alignas(u64) SCR_EL3 {
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static inline void write(SCR_EL3 scr_el3)
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{
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asm("msr scr_el3, %[value]" ::[value] "r"(scr_el3));
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asm volatile("msr scr_el3, %[value]" ::[value] "r"(scr_el3));
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}
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static inline SCR_EL3 read()
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{
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SCR_EL3 scr;
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asm("mrs %[value], scr_el3"
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: [value] "=r"(scr));
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asm volatile("mrs %[value], scr_el3"
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: [value] "=r"(scr));
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return scr;
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}
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@ -890,15 +890,15 @@ struct alignas(u64) SPSR_EL1 {
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static inline void write(SPSR_EL1 spsr_el1)
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{
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asm("msr spsr_el1, %[value]" ::[value] "r"(spsr_el1));
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asm volatile("msr spsr_el1, %[value]" ::[value] "r"(spsr_el1));
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}
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static inline SPSR_EL1 read()
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{
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SPSR_EL1 spsr;
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asm("mrs %[value], spsr_el1"
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: [value] "=r"(spsr));
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asm volatile("mrs %[value], spsr_el1"
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: [value] "=r"(spsr));
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return spsr;
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}
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@ -939,15 +939,15 @@ struct alignas(u64) SPSR_EL2 {
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static inline void write(SPSR_EL2 spsr_el2)
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{
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asm("msr spsr_el2, %[value]" ::[value] "r"(spsr_el2));
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asm volatile("msr spsr_el2, %[value]" ::[value] "r"(spsr_el2));
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}
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static inline SPSR_EL2 read()
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{
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SPSR_EL2 spsr;
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asm("mrs %[value], spsr_el2"
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: [value] "=r"(spsr));
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asm volatile("mrs %[value], spsr_el2"
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: [value] "=r"(spsr));
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return spsr;
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}
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@ -988,15 +988,15 @@ struct alignas(u64) SPSR_EL3 {
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static inline void write(SPSR_EL3 spsr_el3)
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{
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asm("msr spsr_el3, %[value]" ::[value] "r"(spsr_el3));
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asm volatile("msr spsr_el3, %[value]" ::[value] "r"(spsr_el3));
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}
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static inline SPSR_EL3 read()
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{
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SPSR_EL3 spsr;
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asm("mrs %[value], spsr_el3"
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: [value] "=r"(spsr));
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asm volatile("mrs %[value], spsr_el3"
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: [value] "=r"(spsr));
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return spsr;
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}
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@ -1011,7 +1011,7 @@ struct alignas(u64) MAIR_EL1 {
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static inline void write(MAIR_EL1 mair_el1)
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{
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asm("msr mair_el1, %[value]" ::[value] "r"(mair_el1));
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asm volatile("msr mair_el1, %[value]" ::[value] "r"(mair_el1));
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}
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};
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static_assert(sizeof(MAIR_EL1) == 8);
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@ -1029,8 +1029,8 @@ struct ESR_EL1 {
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{
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ESR_EL1 esr_el1;
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asm("mrs %[value], esr_el1"
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: [value] "=r"(esr_el1));
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asm volatile("mrs %[value], esr_el1"
|
||||
: [value] "=r"(esr_el1));
|
||||
|
||||
return esr_el1;
|
||||
}
|
||||
|
@ -1045,8 +1045,8 @@ struct FAR_EL1 {
|
|||
{
|
||||
FAR_EL1 far_el1;
|
||||
|
||||
asm("mrs %[value], far_el1"
|
||||
: [value] "=r"(far_el1));
|
||||
asm volatile("mrs %[value], far_el1"
|
||||
: [value] "=r"(far_el1));
|
||||
|
||||
return far_el1;
|
||||
}
|
||||
|
@ -1359,7 +1359,7 @@ struct alignas(u64) CPACR_EL1 {
|
|||
|
||||
static inline void write(CPACR_EL1 cpacr_el1)
|
||||
{
|
||||
asm("msr cpacr_el1, %[value]" ::[value] "r"(cpacr_el1));
|
||||
asm volatile("msr cpacr_el1, %[value]" ::[value] "r"(cpacr_el1));
|
||||
}
|
||||
};
|
||||
static_assert(sizeof(CPACR_EL1) == 8);
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue