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Kernel/PCI: Convert PCI BAR number to a strong typed enum class
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parent
f510c0ba04
commit
bb6f61ee5d
10 changed files with 26 additions and 17 deletions
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@ -94,10 +94,10 @@ u32 get_BAR5(Address address)
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return read32(address, PCI::RegisterOffset::BAR5);
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}
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u32 get_BAR(Address address, u8 bar)
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u32 get_BAR(Address address, HeaderType0BaseRegister pci_bar)
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{
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VERIFY(bar <= 5);
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switch (bar) {
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VERIFY(to_underlying(pci_bar) <= 5);
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switch (to_underlying(pci_bar)) {
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case 0:
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return get_BAR0(address);
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case 1:
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@ -138,11 +138,11 @@ static u8 read8_offsetted(Address address, u32 field) { return Access::the().rea
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static u16 read16_offsetted(Address address, u32 field) { return Access::the().read16_field(address, field); }
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static u32 read32_offsetted(Address address, u32 field) { return Access::the().read32_field(address, field); }
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size_t get_BAR_space_size(Address address, u8 bar_number)
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size_t get_BAR_space_size(Address address, HeaderType0BaseRegister pci_bar)
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{
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// See PCI Spec 2.3, Page 222
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VERIFY(bar_number < 6);
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u8 field = to_underlying(PCI::RegisterOffset::BAR0) + (bar_number << 2);
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VERIFY(to_underlying(pci_bar) < 6);
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u8 field = to_underlying(PCI::RegisterOffset::BAR0) + (to_underlying(pci_bar) << 2);
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u32 bar_reserved = read32_offsetted(address, field);
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write32_offsetted(address, field, 0xFFFFFFFF);
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u32 space_size = read32_offsetted(address, field);
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@ -31,8 +31,8 @@ u32 get_BAR2(Address);
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u32 get_BAR3(Address);
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u32 get_BAR4(Address);
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u32 get_BAR5(Address);
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u32 get_BAR(Address address, u8 bar);
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size_t get_BAR_space_size(Address, u8);
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u32 get_BAR(Address address, HeaderType0BaseRegister);
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size_t get_BAR_space_size(Address, HeaderType0BaseRegister);
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void enable_bus_mastering(Address);
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void disable_bus_mastering(Address);
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void enable_io_space(Address);
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@ -21,6 +21,15 @@ enum class HeaderType {
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Bridge = 1,
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};
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enum class HeaderType0BaseRegister {
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BAR0 = 0,
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BAR1,
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BAR2,
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BAR3,
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BAR4,
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BAR5,
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};
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enum class RegisterOffset {
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VENDOR_ID = 0x00, // word
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DEVICE_ID = 0x02, // word
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