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Kernel: Add CPUFeature enumeration for Aarch64 CPUs
Also, enumeration name & description mappings are provided along.
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Kernel/Arch/aarch64/CPUID.cpp
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Kernel/Arch/aarch64/CPUID.cpp
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Kernel/Arch/aarch64/CPUID.h
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Kernel/Arch/aarch64/CPUID.h
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/*
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* Copyright (c) 2023, Konrad <konrad@serenityos.org>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/ArbitrarySizedEnum.h>
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#include <AK/Types.h>
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#include <AK/UFixedBigInt.h>
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#include <AK/Platform.h>
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VALIDATE_IS_AARCH64()
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namespace Kernel {
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// https://developer.arm.com/downloads/-/exploration-tools/feature-names-for-a-profile
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AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u256,
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// 2022 Architecture Extensions
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ABLE = CPUFeature(1u) << 0u, // Address Breakpoint Linking extension
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ADERR = CPUFeature(1u) << 1u, // RASv2 Additional Error syndrome reporting, for Device memory
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ANERR = CPUFeature(1u) << 2u, // RASv2 Additional Error syndrome reporting, for Normal memory
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AIE = CPUFeature(1u) << 3u, // Memory Attribute Index Enhancement
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B16B16 = CPUFeature(1u) << 4u, // Non-widening BFloat16 to BFloat16 arithmetic for SVE2.1 and SME2.1
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CLRBHB = CPUFeature(1u) << 5u, // A new instruction CLRBHB is added in HINT space
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CHK = CPUFeature(1u) << 6u, // Detect when Guarded Control Stacks are implemented
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CSSC = CPUFeature(1u) << 7u, // Common Short Sequence Compression scalar integer instructions
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CSV2_3 = CPUFeature(1u) << 8u, // New identification mechanism for Branch History information
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D128 = CPUFeature(1u) << 9u, // 128-bit Translation Tables, 56 bit PA
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Debugv8p9 = CPUFeature(1u) << 10u, // Debug 2022
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DoubleFault2 = CPUFeature(1u) << 11u, // Error exception routing extensions.
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EBEP = CPUFeature(1u) << 12u, // Exception-based event profiling
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ECBHB = CPUFeature(1u) << 13u, // Imposes restrictions on branch history speculation around exceptions
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ETEv1p3 = CPUFeature(1u) << 14u, // ETE support for v9.3
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FGT2 = CPUFeature(1u) << 15u, // Fine-grained traps 2
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GCS = CPUFeature(1u) << 16u, // Guarded Control Stack Extension
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HAFT = CPUFeature(1u) << 17u, // Hardware managed Access Flag for Table descriptors
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ITE = CPUFeature(1u) << 18u, // Instrumentation trace extension
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LRCPC3 = CPUFeature(1u) << 19u, // Load-Acquire RCpc instructions version 3
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LSE128 = CPUFeature(1u) << 20u, // 128-bit Atomics
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LVA3 = CPUFeature(1u) << 21u, // 56-bit VA
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MEC = CPUFeature(1u) << 22u, // Memory Encryption Contexts
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MTE4 = CPUFeature(1u) << 23u, // Support for Canonical tag checking, reporting of all non-address bits on a fault, Store-only Tag checking, Memory tagging with Address tagging disabled
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MTE_CANONICAL_TAGS = CPUFeature(1u) << 24u, // Support for Canonical tag checking
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MTE_TAGGED_FAR = CPUFeature(1u) << 25u, // Support for reporting of all non-address bits on a fault
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MTE_STORE_ONLY = CPUFeature(1u) << 26u, // Support for Store-only Tag checking
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MTE_NO_ADDRESS_TAGS = CPUFeature(1u) << 27u, // Support for Memory tagging with Address tagging disabled
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MTE_ASYM_FAULT = CPUFeature(1u) << 28u, // Asymmetric Tag Check Fault handling
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MTE_ASYNC = CPUFeature(1u) << 29u, // Asynchronous Tag Check Fault handling
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MTE_PERM = CPUFeature(1u) << 30u, // Allocation tag access permission
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PCSRv8p9 = CPUFeature(1u) << 31u, // PCSR disable control
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PIE = CPUFeature(1u) << 32u, // Permission model enhancements
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POE = CPUFeature(1u) << 33u, // Permission model enhancements
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S1PIE = CPUFeature(1u) << 34u, // Permission model enhancements
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S2PIE = CPUFeature(1u) << 35u, // Permission model enhancements
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S1POE = CPUFeature(1u) << 36u, // Permission model enhancements
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S2POE = CPUFeature(1u) << 37u, // Permission model enhancements
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PMUv3p9 = CPUFeature(1u) << 38u, // EL0 access controls for PMU event counters
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PMUv3_EDGE = CPUFeature(1u) << 39u, // PMU event edge detection
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PMUv3_ICNTR = CPUFeature(1u) << 40u, // PMU instruction counter
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PMUv3_SS = CPUFeature(1u) << 41u, // PMU snapshot
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PRFMSLC = CPUFeature(1u) << 42u, // Prefetching enhancements
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PFAR = CPUFeature(1u) << 43u, // Physical Fault Address Extension [NOTE: not yet listed]
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RASv2 = CPUFeature(1u) << 44u, // Reliability, Availability, and Serviceability (RAS) Extension version 2
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RPZ = CPUFeature(1u) << 45u, // ? [NOTE: not yet listed]
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RPRFM = CPUFeature(1u) << 46u, // RPRFM range prefetch hint instruction
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SCTLR2 = CPUFeature(1u) << 47u, // Extension to SCTLR_ELx
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SEBEP = CPUFeature(1u) << 48u, // Synchronous Exception-based event profiling
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SME_F16F16 = CPUFeature(1u) << 49u, // Non-widening half-precision FP16 to FP16 arithmetic for SME2.1
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SME2 = CPUFeature(1u) << 50u, // Scalable Matrix Extension version 2
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SME2p1 = CPUFeature(1u) << 51u, // Scalable Matrix Extension version 2.1
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SPECRES2 = CPUFeature(1u) << 52u, // Adds new Clear Other Speculative Predictions instruction
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SPMU = CPUFeature(1u) << 53u, // System PMU
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SPEv1p4 = CPUFeature(1u) << 54u, // Additional SPE events
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SPE_FDS = CPUFeature(1u) << 55u, // SPE filtering by data source
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SVE2p1 = CPUFeature(1u) << 56u, // Scalable Vector Extension version SVE2.1
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SYSINSTR128 = CPUFeature(1u) << 57u, // 128-bit System instructions
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SYSREG128 = CPUFeature(1u) << 58u, // 128-bit System registers
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TCR2 = CPUFeature(1u) << 59u, // Extension to TCR_ELx
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THE = CPUFeature(1u) << 60u, // Translation Hardening Extension
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TRBE_EXT = CPUFeature(1u) << 61u, // Represents TRBE external mode
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TRBE_MPAM = CPUFeature(1u) << 62u, // Trace Buffer MPAM extensions
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// 2021 Architecture Extensions
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CMOW = CPUFeature(1u) << 63u, // Control for cache maintenance permission
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CONSTPACFIELD = CPUFeature(1u) << 64u, // PAC Algorithm enhancement
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Debugv8p8 = CPUFeature(1u) << 65u, // Debug v8.8
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HBC = CPUFeature(1u) << 66u, // Hinted conditional branches
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HPMN0 = CPUFeature(1u) << 67u, // Setting of MDCR_EL2.HPMN to zero
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NMI = CPUFeature(1u) << 68u, // Non-maskable Interrupts
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GICv3_NMI = CPUFeature(1u) << 69u, // Non-maskable Interrupts
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MOPS = CPUFeature(1u) << 70u, // Standardization of memory operations
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PACQARMA3 = CPUFeature(1u) << 71u, // Pointer authentication - QARMA3 algorithm
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PMUv3_TH = CPUFeature(1u) << 72u, // Event counting threshold
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PMUv3p8 = CPUFeature(1u) << 73u, // Armv8.8 PMU Extensions
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PMUv3_EXT64 = CPUFeature(1u) << 74u, // Optional 64-bit external interface to the Performance Monitors
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PMUv3_EXT32 = CPUFeature(1u) << 75u, // Represents the original mostly 32-bit external interface to the Performance Monitors
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RNG_TRAP = CPUFeature(1u) << 76u, // Trapping support for RNDR and RNDRRS
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SPEv1p3 = CPUFeature(1u) << 77u, // Armv8.8 Statistical Profiling Extensions
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TIDCP1 = CPUFeature(1u) << 78u, // EL0 use of IMPLEMENTATION DEFINED functionality
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BRBEv1p1 = CPUFeature(1u) << 79u, // Branch Record Buffer Extensions version 1.1
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// 2020 Architecture Extensions
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AFP = CPUFeature(1u) << 80u, // Alternate floating-point behavior
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HCX = CPUFeature(1u) << 81u, // Support for the HCRX_EL2 register
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LPA2 = CPUFeature(1u) << 82u, // Larger physical address for 4KB and 16KB translation granules
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LS64 = CPUFeature(1u) << 83u, // Support for 64 byte loads/stores without return
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LS64_V = CPUFeature(1u) << 84u, // Support for 64-byte stores with return
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LS64_ACCDATA = CPUFeature(1u) << 85u, // Support for 64-byte EL0 stores with return
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MTE3 = CPUFeature(1u) << 86u, // MTE Asymmetric Fault Handling
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PAN3 = CPUFeature(1u) << 87u, // Support for SCTLR_ELx.EPAN
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PMUv3p7 = CPUFeature(1u) << 88u, // Armv8.7 PMU Extensions
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RPRES = CPUFeature(1u) << 89u, // Increased precision of Reciprocal Estimate and Reciprocal Square Root Estimate
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RME = CPUFeature(1u) << 90u, // Realm Management Extension
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SME_FA64 = CPUFeature(1u) << 91u, // Additional instructions for the SME Extension
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SME_F64F64 = CPUFeature(1u) << 92u, // Additional instructions for the SME Extension
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SME_I16I64 = CPUFeature(1u) << 93u, // Additional instructions for the SME Extension
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EBF16 = CPUFeature(1u) << 94u, // Additional instructions for the SME Extension
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SPEv1p2 = CPUFeature(1u) << 95u, // Armv8.7 SPE
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WFxT = CPUFeature(1u) << 96u, // WFE and WFI instructions with timeout
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XS = CPUFeature(1u) << 97u, // XS attribute
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BRBE = CPUFeature(1u) << 98u, // Branch Record Buffer Extensions
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// Features introduced prior to 2020
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AdvSIMD = CPUFeature(1u) << 99u, // Advanced SIMD Extension
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AES = CPUFeature(1u) << 100u, // Advanced SIMD AES instructions
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PMULL = CPUFeature(1u) << 101u, // Advanced SIMD PMULL instructions; ARMv8.0-AES is split into AES and PMULL
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CP15SDISABLE2 = CPUFeature(1u) << 102u, // CP15DISABLE2
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CSV2 = CPUFeature(1u) << 103u, // Cache Speculation Variant 2
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CSV2_1p1 = CPUFeature(1u) << 104u, // Cache Speculation Variant 2 version 1.1
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CSV2_1p2 = CPUFeature(1u) << 105u, // Cache Speculation Variant 2 version 1.2
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CSV2_2 = CPUFeature(1u) << 106u, // Cache Speculation Variant 2 version 2 [NOTE: name mistake in source!]
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CSV3 = CPUFeature(1u) << 107u, // Cache Speculation Variant 3
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DGH = CPUFeature(1u) << 108u, // Data Gathering Hint
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DoubleLock = CPUFeature(1u) << 109u, // Double Lock
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ETS = CPUFeature(1u) << 110u, // Enhanced Translation Synchronization
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FP = CPUFeature(1u) << 111u, // Floating point extension
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IVIPT = CPUFeature(1u) << 112u, // The IVIPT Extension
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PCSRv8 = CPUFeature(1u) << 113u, // PC Sample-base Profiling extension (not EL3 and EL2)
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SPECRES = CPUFeature(1u) << 114u, // Speculation restriction instructions
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RAS = CPUFeature(1u) << 115u, // Reliability, Availability, and Serviceability (RAS) Extension
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SB = CPUFeature(1u) << 116u, // Speculation barrier
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SHA1 = CPUFeature(1u) << 117u, // Advanced SIMD SHA1 instructions
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SHA256 = CPUFeature(1u) << 118u, // Advanced SIMD SHA256 instructions; Split ARMv8.2-SHA into SHA-256, SHA-512 and SHA-3
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SSBS = CPUFeature(1u) << 119u, // Speculative Store Bypass Safe Instruction; ARMv8.0-SSBS is split into SSBS and SSBS2
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SSBS2 = CPUFeature(1u) << 120u, // MRS and MSR instructions for SSBS; ARMv8.0-SSBS is split into SSBS and SSBS2
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CRC32 = CPUFeature(1u) << 121u, // CRC32 instructions
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nTLBPA = CPUFeature(1u) << 122u, // No intermediate caching by output address in TLB
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Debugv8p1 = CPUFeature(1u) << 123u, // Debug with VHE
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HPDS = CPUFeature(1u) << 124u, // Hierarchical permission disables in translation tables
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LOR = CPUFeature(1u) << 125u, // Limited ordering regions
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LSE = CPUFeature(1u) << 126u, // Large System Extensions
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PAN = CPUFeature(1u) << 127u, // Privileged access-never
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PMUv3p1 = CPUFeature(1u) << 128u, // PMU extensions version 3.1
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RDM = CPUFeature(1u) << 129u, // Rounding double multiply accumulate
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HAFDBS = CPUFeature(1u) << 130u, // Hardware updates to access flag and dirty state in translation tables
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VHE = CPUFeature(1u) << 131u, // Virtualization Host Extensions
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VMID16 = CPUFeature(1u) << 132u, // 16-bit VMID
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AA32BF16 = CPUFeature(1u) << 133u, // AArch32 BFloat16 instructions
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AA32HPD = CPUFeature(1u) << 134u, // AArch32 Hierarchical permission disables
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AA32I8MM = CPUFeature(1u) << 135u, // AArch32 Int8 Matrix Multiplication
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PAN2 = CPUFeature(1u) << 136u, // AT S1E1R and AT S1E1W instruction variants for PAN
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BF16 = CPUFeature(1u) << 137u, // AARch64 BFloat16 instructions
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DPB2 = CPUFeature(1u) << 138u, // DC CVADP instruction
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DPB = CPUFeature(1u) << 139u, // DC CVAP instruction
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Debugv8p2 = CPUFeature(1u) << 140u, // ARMv8.2 Debug
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DotProd = CPUFeature(1u) << 141u, // Advanced SIMD Int8 dot product instructions
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EVT = CPUFeature(1u) << 142u, // Enhanced Virtualization Traps
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F32MM = CPUFeature(1u) << 143u, // SVE single-precision floating-point matrix multiply instruction
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F64MM = CPUFeature(1u) << 144u, // SVE double-precision floating-point matrix multiply instruction
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FHM = CPUFeature(1u) << 145u, // Half-precision floating-point FMLAL instructions
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FP16 = CPUFeature(1u) << 146u, // Half-precision floating-point data processing
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I8MM = CPUFeature(1u) << 147u, // Int8 Matrix Multiplication
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IESB = CPUFeature(1u) << 148u, // Implicit Error synchronization event
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LPA = CPUFeature(1u) << 149u, // Large PA and IPA support
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LSMAOC = CPUFeature(1u) << 150u, // Load/Store instruction multiple atomicity and ordering controls
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LVA = CPUFeature(1u) << 151u, // Large VA support
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MPAM = CPUFeature(1u) << 152u, // Memory Partitioning and Monitoring
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PCSRv8p2 = CPUFeature(1u) << 153u, // PC Sample-based profiling version 8.2
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SHA3 = CPUFeature(1u) << 154u, // Advanced SIMD EOR3, RAX1, XAR, and BCAX instructions; Split ARMv8.2-SHA into SHA-256, SHA-512 and SHA-3
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SHA512 = CPUFeature(1u) << 155u, // Advanced SIMD SHA512 instructions; Split ARMv8.2-SHA into SHA-256, SHA-512 and SHA-3
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SM3 = CPUFeature(1u) << 156u, // Advanced SIMD SM3 instructions; Split into SM3 and SM4
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SM4 = CPUFeature(1u) << 157u, // Advanced SIMD SM4 instructions; Split into SM3 and SM4
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SPE = CPUFeature(1u) << 158u, // Statistical Profiling Extension
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SVE = CPUFeature(1u) << 159u, // Scalable Vector Extension
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TTCNP = CPUFeature(1u) << 160u, // Common not private translations
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HPDS2 = CPUFeature(1u) << 161u, // Heirarchical permission disables in translation tables 2
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XNX = CPUFeature(1u) << 162u, // Execute-never control distinction by Exception level at stage 2
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UAO = CPUFeature(1u) << 163u, // Unprivileged Access Override control
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VPIPT = CPUFeature(1u) << 164u, // VMID-aware PIPT instruction cache
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CCIDX = CPUFeature(1u) << 165u, // Extended cache index
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FCMA = CPUFeature(1u) << 166u, // Floating-point FCMLA and FCADD instructions
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DoPD = CPUFeature(1u) << 167u, // Debug over Powerdown
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EPAC = CPUFeature(1u) << 168u, // Enhanced Pointer authentication
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FPAC = CPUFeature(1u) << 169u, // Faulting on pointer authentication instructions
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FPACCOMBINE = CPUFeature(1u) << 170u, // Faulting on combined pointer authentication instructions
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JSCVT = CPUFeature(1u) << 171u, // JavaScript FJCVTS conversion instruction
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LRCPC = CPUFeature(1u) << 172u, // Load-acquire RCpc instructions
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NV = CPUFeature(1u) << 173u, // Nested virtualization
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PACQARMA5 = CPUFeature(1u) << 174u, // Pointer authentication - QARMA5 algorithm
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PACIMP = CPUFeature(1u) << 175u, // Pointer authentication - IMPLEMENTATION DEFINED algorithm
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PAuth = CPUFeature(1u) << 176u, // Pointer authentication
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PAuth2 = CPUFeature(1u) << 177u, // Enhancements to pointer authentication
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SPEv1p1 = CPUFeature(1u) << 178u, // Statistical Profiling Extensions version 1.1
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AMUv1 = CPUFeature(1u) << 179u, // Activity Monitors Extension
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CNTSC = CPUFeature(1u) << 180u, // Generic Counter Scaling
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Debugv8p4 = CPUFeature(1u) << 181u, // Debug relaxations and extensions version 8.4
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DoubleFault = CPUFeature(1u) << 182u, // Double Fault Extension
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DIT = CPUFeature(1u) << 183u, // Data Independent Timing instructions
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FlagM = CPUFeature(1u) << 184u, // Condition flag manipulation
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IDST = CPUFeature(1u) << 185u, // ID space trap handling
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LRCPC2 = CPUFeature(1u) << 186u, // Load-acquire RCpc instructions version 2
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LSE2 = CPUFeature(1u) << 187u, // Large System Extensions version 2
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NV2 = CPUFeature(1u) << 188u, // Enhanced support for nested virtualization
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PMUv3p4 = CPUFeature(1u) << 189u, // PMU extension version 3.4
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RASv1p1 = CPUFeature(1u) << 190u, // Reliability, Availability, and Serviceability (RAS) Extension version 1.1
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S2FWB = CPUFeature(1u) << 191u, // Stage 2 forced write-back
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SEL2 = CPUFeature(1u) << 192u, // Secure EL2
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TLBIOS = CPUFeature(1u) << 193u, // TLB invalidate outer-shared instructions; Split into TLBIOS and TLBIRANGE
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TLBIRANGE = CPUFeature(1u) << 194u, // TLB range invalidate range instructions; Split into TLBIOS and TLBIRANGE
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TRF = CPUFeature(1u) << 195u, // Self hosted Trace Extensions
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TTL = CPUFeature(1u) << 196u, // Translation Table Level
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BBM = CPUFeature(1u) << 197u, // Translation table break before make levels
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TTST = CPUFeature(1u) << 198u, // Small translation tables
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BTI = CPUFeature(1u) << 199u, // Branch target identification
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FlagM2 = CPUFeature(1u) << 200u, // Condition flag manipulation version 2
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ExS = CPUFeature(1u) << 201u, // Disabling context synchronizing exception entry and exit
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E0PD = CPUFeature(1u) << 202u, // Preventing EL0 access to halves of address maps
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FRINTTS = CPUFeature(1u) << 203u, // FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions
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GTG = CPUFeature(1u) << 204u, // Guest translation granule size
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MTE = CPUFeature(1u) << 205u, // Instruction-only Memory Tagging Extension
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MTE2 = CPUFeature(1u) << 206u, // Full Memory Tagging Extension
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PMUv3p5 = CPUFeature(1u) << 207u, // PMU Extension version 3.5
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RNG = CPUFeature(1u) << 208u, // Random number generator
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AMUv1p1 = CPUFeature(1u) << 209u, // Activity Monitors Extension version 1.1
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ECV = CPUFeature(1u) << 210u, // Enhanced counter virtualization
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FGT = CPUFeature(1u) << 211u, // Fine Grain Traps
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MPAMv0p1 = CPUFeature(1u) << 212u, // Memory Partitioning and Monitoring version 0.1
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MPAMv1p1 = CPUFeature(1u) << 213u, // Memory Partitioning and Monitoring version 1.1
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MTPMU = CPUFeature(1u) << 214u, // Multi-threaded PMU Extensions
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TWED = CPUFeature(1u) << 215u, // Delayed trapping of WFE
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ETMv4 = CPUFeature(1u) << 216u, // Embedded Trace Macrocell version4
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ETMv4p1 = CPUFeature(1u) << 217u, // Embedded Trace Macrocell version 4.1
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ETMv4p2 = CPUFeature(1u) << 218u, // Embedded Trace Macrocell version 4.2
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ETMv4p3 = CPUFeature(1u) << 219u, // Embedded Trace Macrocell version 4.3
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ETMv4p4 = CPUFeature(1u) << 220u, // Embedded Trace Macrocell version 4.3
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ETMv4p5 = CPUFeature(1u) << 221u, // Embedded Trace Macrocell version 4.4
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ETMv4p6 = CPUFeature(1u) << 222u, // Embedded Trace Macrocell version 4.5
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GICv3 = CPUFeature(1u) << 223u, // Generic Interrupt Controller version 3
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GICv3p1 = CPUFeature(1u) << 224u, // Generic Interrupt Controller version 3.1
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// Note: cf. https://developer.arm.com/documentation/ihi0069/h/?lang=en
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GICv3_LEGACY = CPUFeature(1u) << 225u, // Support for GICv2 legacy operation
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GICv3_TDIR = CPUFeature(1u) << 226u, // Trapping Non-secure EL1 writes to ICV_DIR
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GICv4 = CPUFeature(1u) << 227u, // Generic Interrupt Controller version 4
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GICv4p1 = CPUFeature(1u) << 228u, // Generic Interrupt Controller version 4.1
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PMUv3 = CPUFeature(1u) << 229u, // PMU extension version 3
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ETE = CPUFeature(1u) << 230u, // Embedded Trace Extension
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ETEv1p1 = CPUFeature(1u) << 231u, // Embedded Trace Extension, version 1.1
|
||||
SVE2 = CPUFeature(1u) << 232u, // SVE version 2
|
||||
SVE_AES = CPUFeature(1u) << 233u, // SVE AES instructions
|
||||
SVE_PMULL128 = CPUFeature(1u) << 234u, // SVE PMULL instructions; SVE2-AES is split into AES and PMULL support
|
||||
SVE_BitPerm = CPUFeature(1u) << 235u, // SVE Bit Permute
|
||||
SVE_SHA3 = CPUFeature(1u) << 236u, // SVE SHA-3 instructions
|
||||
SVE_SM4 = CPUFeature(1u) << 237u, // SVE SM4 instructions
|
||||
TME = CPUFeature(1u) << 238u, // Transactional Memory Extension
|
||||
TRBE = CPUFeature(1u) << 239u, // Trace Buffer Extension
|
||||
SME = CPUFeature(1u) << 240u, // Scalable Matrix Extension
|
||||
|
||||
__End = CPUFeature(1u) << 255u);
|
||||
|
||||
StringView cpu_feature_to_name(CPUFeature::Type const&);
|
||||
StringView cpu_feature_to_description(CPUFeature::Type const&);
|
||||
|
||||
}
|
|
@ -449,6 +449,7 @@ elseif("${SERENITY_ARCH}" STREQUAL "aarch64")
|
|||
|
||||
Arch/aarch64/boot.S
|
||||
Arch/aarch64/BootPPMParser.cpp
|
||||
Arch/aarch64/CPUID.cpp
|
||||
Arch/aarch64/CrashHandler.cpp
|
||||
Arch/aarch64/CurrentTime.cpp
|
||||
Arch/aarch64/Dummy.cpp
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue