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LibX86: Disassemble most FPU instructions starting with D9

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Some of these don't just use the REG bits of the mod/rm byte
as slashes, but also the R/M bits to have up to 9 different
instructions per opcode/slash combination (1 opcode requires
that MOD is != 11, the other 8 have MODE == 11).

This is done by making the slashes table two levels deep for
these cases.

Some of this is cosmetic (e.g "FST st0" has no effect already,
but its bit pattern gets disassembled as "FNOP"), but for
most uses it isn't.

FSTENV and FSTCW have an extraordinary 0x9b prefix. This is
not yet handled in this patch.
This commit is contained in:
Nico Weber 2020-07-28 11:09:54 -04:00 • committed by Andreas Kling
parent 6f12ab3ced
commit c99a3efc5b
5 changed files with 209 additions and 13 deletions
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36
Libraries/LibX86/Interpreter.h
View file

@ -164,6 +164,42 @@ public:
virtual void FSUBR_RM32(const Instruction&) = 0;
virtual void FDIV_RM32(const Instruction&) = 0;
virtual void FDIVR_RM32(const Instruction&) = 0;
virtual void FLD_RM32(const Instruction&) = 0;
virtual void FXCH(const Instruction&) = 0;
virtual void FST_RM32(const Instruction&) = 0;
virtual void FNOP(const Instruction&) = 0;
virtual void FSTP_RM32(const Instruction&) = 0;
virtual void FLDENV(const Instruction&) = 0;
virtual void FCHS(const Instruction&) = 0;
virtual void FABS(const Instruction&) = 0;
virtual void FTST(const Instruction&) = 0;
virtual void FXAM(const Instruction&) = 0;
virtual void FLDCW(const Instruction&) = 0;
virtual void FLD1(const Instruction&) = 0;
virtual void FLDL2T(const Instruction&) = 0;
virtual void FLDL2E(const Instruction&) = 0;
virtual void FLDPI(const Instruction&) = 0;
virtual void FLDLG2(const Instruction&) = 0;
virtual void FLDLN2(const Instruction&) = 0;
virtual void FLDZ(const Instruction&) = 0;
virtual void FNSTENV(const Instruction&) = 0;
virtual void F2XM1(const Instruction&) = 0;
virtual void FYL2X(const Instruction&) = 0;
virtual void FPTAN(const Instruction&) = 0;
virtual void FPATAN(const Instruction&) = 0;
virtual void FXTRACT(const Instruction&) = 0;
virtual void FPREM1(const Instruction&) = 0;
virtual void FDECSTP(const Instruction&) = 0;
virtual void FINCSTP(const Instruction&) = 0;
virtual void FNSTCW(const Instruction&) = 0;
virtual void FPREM(const Instruction&) = 0;
virtual void FYL2XP1(const Instruction&) = 0;
virtual void FSQRT(const Instruction&) = 0;
virtual void FSINCOS(const Instruction&) = 0;
virtual void FRNDINT(const Instruction&) = 0;
virtual void FSCALE(const Instruction&) = 0;
virtual void FSIN(const Instruction&) = 0;
virtual void FCOS(const Instruction&) = 0;
virtual void FADD_RM64(const Instruction&) = 0;
virtual void FMUL_RM64(const Instruction&) = 0;
virtual void FCOM_RM64(const Instruction&) = 0;