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https://github.com/RGBCube/serenity
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Everywhere: Fix a variety of typos
Spelling fixes found by `codespell`.
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63c727a4a3
commit
d0a1775369
30 changed files with 38 additions and 38 deletions
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@ -24,7 +24,7 @@ void SoftVPU::LDMXCSR(X86::Instruction const& insn)
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VERIFY((m_mxcsr.mxcsr & 0xFFFF'0000) == 0);
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// Just let the host's SSE (or if not available x87) handle the rounding for us
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// We do not want to accedentally raise an FP-Exception on the host, so we
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// We do not want to accidentally raise an FP-Exception on the host, so we
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// mask all exceptions
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#ifdef __SSE__
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AK::MXCSR temp = m_mxcsr;
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@ -99,7 +99,7 @@ void SoftVPU::MOVLPS_xmm1_xmm2m64(X86::Instruction const& insn)
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m_xmm[xmm1].puqw[0] = m_xmm[insn.modrm().rm()].puqw[1];
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} else {
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// FIXME: Shadows
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// Note: Technically we are transfereing two packed floats not a quad word
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// Note: Technically we are transferring two packed floats not a quad word
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m_xmm[xmm1].puqw[0] = insn.modrm().read64(m_cpu, insn).value();
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}
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}
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@ -108,7 +108,7 @@ void SoftVPU::MOVLPS_m64_xmm2(X86::Instruction const& insn)
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u8 xmm2 = insn.modrm().reg();
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// FIXME: This might not hold true for SSE2 or later
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VERIFY(!insn.modrm().is_register());
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// Note: Technically we are transfereing two packed floats not a quad word
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// Note: Technically we are transferring two packed floats not a quad word
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insn.modrm().write64(m_cpu, insn, ValueWithShadow<u64>::create_initialized(m_xmm[xmm2].puqw[0]));
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}
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@ -166,7 +166,7 @@ void SoftVPU::MOVHPS_xmm1_xmm2m64(X86::Instruction const& insn)
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m_xmm[xmm1].puqw[1] = m_xmm[insn.modrm().rm()].puqw[0];
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} else {
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// FIXME: Shadows
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// Note: Technically we are transfereing two packed floats not a quad word
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// Note: Technically we are transferring two packed floats not a quad word
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m_xmm[xmm1].puqw[1] = insn.modrm().read64(m_cpu, insn).value();
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}
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}
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@ -174,7 +174,7 @@ void SoftVPU::MOVHPS_m64_xmm2(X86::Instruction const& insn)
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{
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u8 xmm1 = insn.modrm().reg();
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VERIFY(!insn.modrm().is_register());
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// Note: Technically we are transfereing two packed floats not a quad word
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// Note: Technically we are transferring two packed floats not a quad word
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insn.modrm().write64(m_cpu, insn, ValueWithShadow<u64>::create_initialized(m_xmm[xmm1].puqw[1]));
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}
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void SoftVPU::MOVAPS_xmm1_xmm2m128(X86::Instruction const& insn)
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@ -202,7 +202,7 @@ void SoftVPU::MOVAPS_xmm1m128_xmm2(X86::Instruction const& insn)
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void SoftVPU::CVTPI2PS_xmm1_mm2m64(X86::Instruction const& insn)
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{
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// FIXME: Raise Precission
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// FIXME: Raise Precision
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// FIXME: Honor Rounding control
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u8 xmm1 = insn.modrm().reg();
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if (insn.modrm().is_register()) {
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@ -218,7 +218,7 @@ void SoftVPU::CVTPI2PS_xmm1_mm2m64(X86::Instruction const& insn)
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}
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void SoftVPU::CVTSI2SS_xmm1_rm32(X86::Instruction const& insn)
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{
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// FIXME: Raise Precission
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// FIXME: Raise Precision
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// FIXME: Shadows
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// FIXME: Honor Rounding Control
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m_xmm[insn.modrm().reg()].ps[0] = (i32)insn.modrm().read32(m_cpu, insn).value();
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