From d5262a540cf7df1d1267afb81caad19f74d633f1 Mon Sep 17 00:00:00 2001 From: Timon Kruiper Date: Mon, 30 Jan 2023 15:42:39 +0100 Subject: [PATCH] Kernel/aarch64: Handle SVC exception by calling syscall_handler The SVC (supervisor call) instruction is used in userland to do syscalls, and this commit adds the handling of syscalls to Interrupts.cpp. --- Kernel/Arch/aarch64/Interrupts.cpp | 4 ++++ Kernel/Arch/aarch64/Registers.h | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/Kernel/Arch/aarch64/Interrupts.cpp b/Kernel/Arch/aarch64/Interrupts.cpp index a8f9b5a89f..26c87817dd 100644 --- a/Kernel/Arch/aarch64/Interrupts.cpp +++ b/Kernel/Arch/aarch64/Interrupts.cpp @@ -18,6 +18,8 @@ namespace Kernel { +extern "C" void syscall_handler(TrapFrame const*); + static void dump_exception_syndrome_register(Aarch64::ESR_EL1 const& esr_el1) { dbgln("Exception Syndrome: EC({:#b}) IL({:#b}) ISS({:#b}) ISS2({:#b})", esr_el1.EC, esr_el1.IL, esr_el1.ISS, esr_el1.ISS2); @@ -87,6 +89,8 @@ extern "C" void exception_common(Kernel::TrapFrame* trap_frame) if (Aarch64::exception_class_is_data_abort(esr_el1.EC) || Aarch64::exception_class_is_instruction_abort(esr_el1.EC)) { auto page_fault = page_fault_from_exception_syndrome_register(VirtualAddress(fault_address), esr_el1); page_fault.handle(*trap_frame->regs); + } else if (Aarch64::exception_class_is_svc_instruction_execution(esr_el1.EC)) { + syscall_handler(trap_frame); } else { dump_registers(*trap_frame->regs); PANIC("Unexpected exception!"); diff --git a/Kernel/Arch/aarch64/Registers.h b/Kernel/Arch/aarch64/Registers.h index dd96a6f82a..096b4672f3 100644 --- a/Kernel/Arch/aarch64/Registers.h +++ b/Kernel/Arch/aarch64/Registers.h @@ -1172,6 +1172,11 @@ static inline bool exception_class_is_data_or_instruction_abort_from_lower_excep return exception_class == 0x20 || exception_class == 0x24; } +static inline bool exception_class_is_svc_instruction_execution(u8 exception_class) +{ + return exception_class == 0x11 || exception_class == 0x15; +} + // D17.2.37 ESR_EL1, Exception Syndrome Register (EL1) // ISS encoding for an exception from a Data Abort // DFSC, bits [5:0]