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https://github.com/RGBCube/serenity
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Kernel: Fix HPET timer not firing in Bochs
* Change the register structures to use the volatile keyword explicitly on the register values. This avoids accidentally omitting it as any access will be guaranteed volatile. * Don't assume we can read/write 64 bit value to the main counter and the comparator. Not all HPET implementations may support this. So, just use 32 bit words to access the registers. This ultimately works around a bug in Bochs 2.6.11 that loses 32 bits of a 64 bit write to a timer's comparator register (it internally writes one half and clears the Tn_VAL_SET_CNF bit, and then because it's cleared it fails to write the second half). * Properly calculate the tick duration in calculate_ticks_in_nanoseconds * As per specification, changing the frequency of one periodic timer requires a restart of all periodic timers as it requires the main counter to be reset.
This commit is contained in:
Tom
Andreas Kling
parent
348cd0fdc1
commit
d5bb5d109b
4 changed files with 158 additions and 95 deletions
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@ -48,58 +48,78 @@ enum class Attributes {
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};
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enum class Configuration {
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Enable = 0x1,
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LegacyReplacementRoute = 0x2
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Enable = 1 << 0,
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LegacyReplacementRoute = 1 << 1
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};
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enum class TimerConfiguration : u32 {
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InterruptType = 1 << 1,
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LevelTriggered = 1 << 1,
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InterruptEnable = 1 << 2,
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TimerType = 1 << 3,
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GeneratePeriodicInterrupt = 1 << 3,
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PeriodicInterruptCapable = 1 << 4,
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Timer64BitsCapable = 1 << 5,
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ValueSet = 1 << 6,
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Force32BitMode = 1 << 7,
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Force32BitMode = 1 << 8,
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FSBInterruptEnable = 1 << 14,
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FSBInterruptDelivery = 1 << 15
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};
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};
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struct [[gnu::packed]] HPETRegister
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{
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volatile u32 low;
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volatile u32 high;
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};
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struct [[gnu::packed]] TimerStructure
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{
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u64 configuration_and_capability;
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u64 comparator_value;
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u64 fsb_interrupt_route;
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volatile u32 capabilities;
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volatile u32 interrupt_routing;
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HPETRegister comparator_value;
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volatile u64 fsb_interrupt_route;
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u64 reserved;
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};
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struct [[gnu::packed]] HPETCapabilityRegister
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{
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u32 attributes; // Note: We must do a 32 bit access to offsets 0x0, or 0x4 only, according to HPET spec.
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u32 main_counter_tick_period;
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u64 reserved;
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};
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struct [[gnu::packed]] HPETRegister
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{
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u64 reg;
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// Note: We must do a 32 bit access to offsets 0x0, or 0x4 only, according to HPET spec.
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volatile u32 attributes;
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volatile u32 main_counter_tick_period;
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u64 reserved;
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};
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struct [[gnu::packed]] HPETRegistersBlock
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{
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union {
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HPETCapabilityRegister capabilities;
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HPETRegister raw_capabilites;
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};
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HPETCapabilityRegister capabilities;
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HPETRegister configuration;
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u64 reserved1;
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HPETRegister interrupt_status;
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u8 reserved[0xF0 - 48];
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u8 reserved2[0xF0 - 0x28];
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HPETRegister main_counter_value;
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u64 reserved3;
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TimerStructure timers[3];
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u8 reserved2[0x400 - 0x160];
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u8 reserved4[0x400 - 0x160];
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};
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static_assert(__builtin_offsetof(HPETRegistersBlock, main_counter_value) == 0xf0);
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static_assert(__builtin_offsetof(HPETRegistersBlock, timers[0]) == 0x100);
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static_assert(__builtin_offsetof(HPETRegistersBlock, timers[1]) == 0x120);
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static u64 read_register_safe64(const HPETRegister& reg)
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{
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// As per 2.4.7 this reads the 64 bit value in a consistent manner
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// using only 32 bit reads
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u32 low, high = reg.high;
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for (;;) {
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low = reg.low;
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u32 new_high = reg.high;
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if (new_high == high)
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break;
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high = new_high;
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}
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return ((u64)high << 32) | (u64)low;
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}
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static HPET* s_hpet;
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static bool hpet_initialized { false };
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@ -135,7 +155,7 @@ bool HPET::test_and_initialize()
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return false;
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}
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}
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s_hpet = new HPET(PhysicalAddress(hpet));
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new HPET(PhysicalAddress(hpet));
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return true;
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}
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@ -147,11 +167,11 @@ bool HPET::check_for_exisiting_periodic_timers()
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auto sdt = map_typed<ACPI::Structures::HPET>(hpet);
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ASSERT(sdt->event_timer_block.address_space == 0);
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auto registers = map_typed<volatile HPETRegistersBlock>(PhysicalAddress(sdt->event_timer_block.address));
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auto registers = map_typed<HPETRegistersBlock>(PhysicalAddress(sdt->event_timer_block.address));
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size_t timers_count = ((registers->raw_capabilites.reg >> 8) & 0x1f) + 1;
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size_t timers_count = ((registers->capabilities.attributes >> 8) & 0x1f) + 1;
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for (size_t index = 0; index < timers_count; index++) {
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if (registers->timers[index].configuration_and_capability & (u32)HPETFlags::TimerConfiguration::PeriodicInterruptCapable)
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if (registers->timers[index].capabilities & (u32)HPETFlags::TimerConfiguration::PeriodicInterruptCapable)
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return true;
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}
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return false;
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@ -159,30 +179,67 @@ bool HPET::check_for_exisiting_periodic_timers()
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void HPET::global_disable()
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{
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registers().configuration.reg = registers().configuration.reg & ~(u32)HPETFlags::Configuration::Enable;
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auto& regs = registers();
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regs.configuration.low = regs.configuration.low & ~(u32)HPETFlags::Configuration::Enable;
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}
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void HPET::global_enable()
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{
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registers().configuration.reg = registers().configuration.reg | (u32)HPETFlags::Configuration::Enable;
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auto& regs = registers();
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regs.configuration.low = regs.configuration.low | (u32)HPETFlags::Configuration::Enable;
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}
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void HPET::set_periodic_comparator_value(const HPETComparator& comparator, u64 value)
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void HPET::update_periodic_comparator_value()
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{
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disable(comparator);
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ASSERT(comparator.is_periodic());
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ASSERT(comparator.comparator_number() <= m_comparators.size());
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volatile auto& timer = registers().timers[comparator.comparator_number()];
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timer.configuration_and_capability = timer.configuration_and_capability | (u32)HPETFlags::TimerConfiguration::ValueSet;
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timer.comparator_value = value;
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enable(comparator);
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// According to 2.3.9.2.2 the only safe way to change the periodic timer frequency
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// is to disable all periodic timers, reset the main counter and each timer's comparator value.
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// This introduces time drift, so it should be avoided unless absolutely necessary.
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global_disable();
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auto& regs = registers();
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u64 previous_main_value = (u64)regs.main_counter_value.low | ((u64)regs.main_counter_value.high << 32);
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regs.main_counter_value.low = 0;
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regs.main_counter_value.high = 0;
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for (auto& comparator : m_comparators) {
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auto& timer = regs.timers[comparator.comparator_number()];
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if (comparator.is_periodic()) {
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// Note that this means we're restarting all periodic timers. There is no
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// way to resume periodic timers properly because we reset the main counter
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// and we can only write the period into the comparator value...
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timer.capabilities = timer.capabilities | (u32)HPETFlags::TimerConfiguration::ValueSet;
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u64 value = frequency() / comparator.ticks_per_second();
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#ifdef HPET_DEBUG
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dbg() << "HPET: Update periodic comparator " << comparator.comparator_number() << " comparator value to " << value << " main value was: " << previous_main_value;
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#endif
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timer.comparator_value.low = (u32)value;
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timer.capabilities = timer.capabilities | (u32)HPETFlags::TimerConfiguration::ValueSet;
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timer.comparator_value.high = (u32)(value >> 32);
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} else {
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// Set the new target comparator value to the delta to the remaining ticks
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u64 current_value = (u64)timer.comparator_value.low | ((u64)timer.comparator_value.high << 32);
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u64 value = current_value - previous_main_value;
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#ifdef HPET_DEBUG
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dbg() << "HPET: Update non-periodic comparator " << comparator.comparator_number() << " comparator value from " << current_value << " to " << value << " main value was: " << previous_main_value;
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#endif
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timer.comparator_value.low = (u32)value;
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timer.comparator_value.high = (u32)(value >> 32);
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}
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}
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global_enable();
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}
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void HPET::set_non_periodic_comparator_value(const HPETComparator& comparator, u64 value)
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void HPET::update_non_periodic_comparator_value(const HPETComparator& comparator)
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{
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ASSERT_INTERRUPTS_DISABLED();
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ASSERT(!comparator.is_periodic());
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ASSERT(comparator.comparator_number() <= m_comparators.size());
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registers().timers[comparator.comparator_number()].comparator_value = main_counter_value() + value;
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auto& regs = registers();
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auto& timer = regs.timers[comparator.comparator_number()];
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u64 value = frequency() / comparator.ticks_per_second();
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// NOTE: If the main counter passes this new value before we finish writing it, we will never receive an interrupt!
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u64 new_counter_value = read_register_safe64(regs.main_counter_value) + value;
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timer.comparator_value.high = (u32)(new_counter_value >> 32);
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timer.comparator_value.low = (u32)new_counter_value;
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}
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void HPET::enable_periodic_interrupt(const HPETComparator& comparator)
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@ -192,10 +249,10 @@ void HPET::enable_periodic_interrupt(const HPETComparator& comparator)
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#endif
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disable(comparator);
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ASSERT(comparator.comparator_number() <= m_comparators.size());
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volatile auto& timer = registers().timers[comparator.comparator_number()];
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auto configuration_and_capability = timer.configuration_and_capability;
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ASSERT(configuration_and_capability & (u32)HPETFlags::TimerConfiguration::PeriodicInterruptCapable);
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timer.configuration_and_capability = configuration_and_capability | (u32)HPETFlags::TimerConfiguration::TimerType;
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auto& timer = registers().timers[comparator.comparator_number()];
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auto capabilities = timer.capabilities;
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ASSERT(capabilities & (u32)HPETFlags::TimerConfiguration::PeriodicInterruptCapable);
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timer.capabilities = capabilities | (u32)HPETFlags::TimerConfiguration::GeneratePeriodicInterrupt;
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enable(comparator);
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}
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void HPET::disable_periodic_interrupt(const HPETComparator& comparator)
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@ -205,10 +262,10 @@ void HPET::disable_periodic_interrupt(const HPETComparator& comparator)
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#endif
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disable(comparator);
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ASSERT(comparator.comparator_number() <= m_comparators.size());
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auto volatile& timer = registers().timers[comparator.comparator_number()];
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auto configuration_and_capability = timer.configuration_and_capability;
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ASSERT(configuration_and_capability & (u32)HPETFlags::TimerConfiguration::PeriodicInterruptCapable);
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timer.configuration_and_capability = configuration_and_capability & ~(u32)HPETFlags::TimerConfiguration::TimerType;
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auto& timer = registers().timers[comparator.comparator_number()];
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auto capabilities = timer.capabilities;
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ASSERT(capabilities & (u32)HPETFlags::TimerConfiguration::PeriodicInterruptCapable);
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timer.capabilities = capabilities & ~(u32)HPETFlags::TimerConfiguration::GeneratePeriodicInterrupt;
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enable(comparator);
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}
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@ -218,8 +275,8 @@ void HPET::disable(const HPETComparator& comparator)
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klog() << "HPET: Disable comparator " << comparator.comparator_number() << ".";
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#endif
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ASSERT(comparator.comparator_number() <= m_comparators.size());
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volatile auto& timer = registers().timers[comparator.comparator_number()];
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timer.configuration_and_capability = timer.configuration_and_capability & ~(u32)HPETFlags::TimerConfiguration::InterruptEnable;
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auto& timer = registers().timers[comparator.comparator_number()];
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timer.capabilities = timer.capabilities & ~(u32)HPETFlags::TimerConfiguration::InterruptEnable;
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}
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void HPET::enable(const HPETComparator& comparator)
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{
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@ -227,13 +284,8 @@ void HPET::enable(const HPETComparator& comparator)
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klog() << "HPET: Enable comparator " << comparator.comparator_number() << ".";
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#endif
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ASSERT(comparator.comparator_number() <= m_comparators.size());
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volatile auto& timer = registers().timers[comparator.comparator_number()];
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timer.configuration_and_capability = timer.configuration_and_capability | (u32)HPETFlags::TimerConfiguration::InterruptEnable;
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}
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u64 HPET::main_counter_value() const
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{
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return registers().main_counter_value.reg;
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auto& timer = registers().timers[comparator.comparator_number()];
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timer.capabilities = timer.capabilities | (u32)HPETFlags::TimerConfiguration::InterruptEnable;
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}
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u64 HPET::frequency() const
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@ -245,8 +297,8 @@ Vector<unsigned> HPET::capable_interrupt_numbers(const HPETComparator& comparato
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{
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ASSERT(comparator.comparator_number() <= m_comparators.size());
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Vector<unsigned> capable_interrupts;
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auto& comparator_registers = (const volatile TimerStructure&)registers().timers[comparator.comparator_number()];
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u32 interrupt_bitfield = comparator_registers.configuration_and_capability >> 32;
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auto& comparator_registers = registers().timers[comparator.comparator_number()];
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u32 interrupt_bitfield = comparator_registers.interrupt_routing;
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for (size_t index = 0; index < 32; index++) {
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if (interrupt_bitfield & 1)
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capable_interrupts.append(index);
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@ -259,8 +311,8 @@ Vector<unsigned> HPET::capable_interrupt_numbers(u8 comparator_number)
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{
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ASSERT(comparator_number <= m_comparators.size());
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Vector<unsigned> capable_interrupts;
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auto& comparator_registers = (const volatile TimerStructure&)registers().timers[comparator_number];
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u32 interrupt_bitfield = comparator_registers.configuration_and_capability >> 32;
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auto& comparator_registers = registers().timers[comparator_number];
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u32 interrupt_bitfield = comparator_registers.interrupt_routing;
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for (size_t index = 0; index < 32; index++) {
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if (interrupt_bitfield & 1)
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capable_interrupts.append(index);
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@ -272,15 +324,15 @@ Vector<unsigned> HPET::capable_interrupt_numbers(u8 comparator_number)
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void HPET::set_comparator_irq_vector(u8 comparator_number, u8 irq_vector)
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{
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ASSERT(comparator_number <= m_comparators.size());
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auto& comparator_registers = (volatile TimerStructure&)registers().timers[comparator_number];
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comparator_registers.configuration_and_capability = comparator_registers.configuration_and_capability | (irq_vector << 9);
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auto& comparator_registers = registers().timers[comparator_number];
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comparator_registers.capabilities = comparator_registers.capabilities | (irq_vector << 9);
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}
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bool HPET::is_periodic_capable(u8 comparator_number) const
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{
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ASSERT(comparator_number <= m_comparators.size());
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auto& comparator_registers = (const volatile TimerStructure&)registers().timers[comparator_number];
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return comparator_registers.configuration_and_capability & (u32)HPETFlags::TimerConfiguration::PeriodicInterruptCapable;
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auto& comparator_registers = registers().timers[comparator_number];
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return comparator_registers.capabilities & (u32)HPETFlags::TimerConfiguration::PeriodicInterruptCapable;
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}
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void HPET::set_comparators_to_optimal_interrupt_state(size_t)
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@ -296,19 +348,20 @@ PhysicalAddress HPET::find_acpi_hpet_registers_block()
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return PhysicalAddress(sdt->event_timer_block.address);
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}
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const volatile HPETRegistersBlock& HPET::registers() const
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const HPETRegistersBlock& HPET::registers() const
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{
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return *(const volatile HPETRegistersBlock*)m_hpet_mmio_region->vaddr().offset(m_physical_acpi_hpet_registers.offset_in_page()).as_ptr();
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return *(const HPETRegistersBlock*)m_hpet_mmio_region->vaddr().offset(m_physical_acpi_hpet_registers.offset_in_page()).as_ptr();
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}
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volatile HPETRegistersBlock& HPET::registers()
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HPETRegistersBlock& HPET::registers()
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{
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return *(volatile HPETRegistersBlock*)m_hpet_mmio_region->vaddr().offset(m_physical_acpi_hpet_registers.offset_in_page()).as_ptr();
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return *(HPETRegistersBlock*)m_hpet_mmio_region->vaddr().offset(m_physical_acpi_hpet_registers.offset_in_page()).as_ptr();
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}
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u64 HPET::calculate_ticks_in_nanoseconds() const
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{
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return ABSOLUTE_MAXIMUM_COUNTER_TICK_PERIOD / registers().capabilities.main_counter_tick_period;
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// ABSOLUTE_MAXIMUM_COUNTER_TICK_PERIOD == 100 nanoseconds
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return ((u64)registers().capabilities.main_counter_tick_period * 100ull) / ABSOLUTE_MAXIMUM_COUNTER_TICK_PERIOD;
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}
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HPET::HPET(PhysicalAddress acpi_hpet)
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@ -316,27 +369,36 @@ HPET::HPET(PhysicalAddress acpi_hpet)
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, m_physical_acpi_hpet_registers(find_acpi_hpet_registers_block())
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, m_hpet_mmio_region(MM.allocate_kernel_region(m_physical_acpi_hpet_registers.page_base(), PAGE_SIZE, "HPET MMIO", Region::Access::Read | Region::Access::Write))
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{
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s_hpet = this; // Make available as soon as possible so that IRQs can use it
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auto sdt = map_typed<const volatile ACPI::Structures::HPET>(m_physical_acpi_hpet_table);
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m_vendor_id = sdt->pci_vendor_id;
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m_minimum_tick = sdt->mininum_clock_tick;
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klog() << "HPET: Minimum clock tick - " << m_minimum_tick;
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auto& regs = registers();
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// Note: We must do a 32 bit access to offsets 0x0, or 0x4 only.
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size_t timers_count = ((registers().raw_capabilites.reg >> 8) & 0x1f) + 1;
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size_t timers_count = ((regs.capabilities.attributes >> 8) & 0x1f) + 1;
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klog() << "HPET: Timers count - " << timers_count;
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klog() << "HPET: Main counter size: " << ((regs.capabilities.attributes & (u32)HPETFlags::Attributes::Counter64BitCapable) ? "64 bit" : "32 bit");
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for (size_t i = 0; i < timers_count; i++) {
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bool capable_64_bit = regs.timers[i].capabilities & (u32)HPETFlags::TimerConfiguration::Timer64BitsCapable;
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klog() << "HPET: Timer[" << i << "] comparator size: " << (capable_64_bit ? "64 bit" : "32 bit") << " mode: " << ((!capable_64_bit || (regs.timers[i].capabilities & (u32)HPETFlags::TimerConfiguration::Force32BitMode)) ? "32 bit" : "64 bit");
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}
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ASSERT(timers_count >= 2);
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auto* capabilities_register = (const volatile HPETCapabilityRegister*)®isters().raw_capabilites.reg;
|
||||
|
||||
global_disable();
|
||||
|
||||
m_frequency = NANOSECOND_PERIOD_TO_HERTZ(calculate_ticks_in_nanoseconds());
|
||||
klog() << "HPET: frequency " << m_frequency << " Hz (" << MEGAHERTZ_TO_HERTZ(m_frequency) << " MHz)";
|
||||
ASSERT(capabilities_register->main_counter_tick_period <= ABSOLUTE_MAXIMUM_COUNTER_TICK_PERIOD);
|
||||
klog() << "HPET: frequency " << m_frequency << " Hz (" << MEGAHERTZ_TO_HERTZ(m_frequency) << " MHz) resolution: " << calculate_ticks_in_nanoseconds() << "ns";
|
||||
ASSERT(regs.capabilities.main_counter_tick_period <= ABSOLUTE_MAXIMUM_COUNTER_TICK_PERIOD);
|
||||
|
||||
// Reset the counter, just in case...
|
||||
registers().main_counter_value.reg = 0;
|
||||
if (registers().raw_capabilites.reg & (u32)HPETFlags::Attributes::LegacyReplacementRouteCapable)
|
||||
registers().configuration.reg = registers().configuration.reg | (u32)HPETFlags::Configuration::LegacyReplacementRoute;
|
||||
regs.main_counter_value.high = 0;
|
||||
regs.main_counter_value.low = 0;
|
||||
if (regs.capabilities.attributes & (u32)HPETFlags::Attributes::LegacyReplacementRouteCapable)
|
||||
regs.configuration.low = regs.configuration.low | (u32)HPETFlags::Configuration::LegacyReplacementRoute;
|
||||
|
||||
m_comparators.append(HPETComparator::create(0, 0, is_periodic_capable(0)));
|
||||
m_comparators.append(HPETComparator::create(1, 8, is_periodic_capable(1)));
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue