From d62bd3c63560382345ad80a3803241012740798a Mon Sep 17 00:00:00 2001 From: Timon Kruiper Date: Fri, 19 Aug 2022 19:11:06 +0200 Subject: [PATCH] Kernel/aarch64: Properly initialize T0SZ and T1SZ fields in TCR_EL1 By default these 2 fields were zero, which made it rely on implementation defined behavior whether these fields internally would be set to the correct value. The ARM processor in the Raspberry PI (and QEMU 6.x) would actually fixup these values, whereas QEMU 7.x now does not do that anymore, and a translation fault would be generated instead. For more context see the relevant QEMU issue: - https://gitlab.com/qemu-project/qemu/-/issues/1157 Fixes #14856 --- Kernel/Arch/aarch64/MMU.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Kernel/Arch/aarch64/MMU.cpp b/Kernel/Arch/aarch64/MMU.cpp index 8575b1de1e..36b5558ab2 100644 --- a/Kernel/Arch/aarch64/MMU.cpp +++ b/Kernel/Arch/aarch64/MMU.cpp @@ -164,10 +164,12 @@ static void activate_mmu() tcr_el1.SH1 = Aarch64::TCR_EL1::InnerShareable; tcr_el1.ORGN1 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable; tcr_el1.IRGN1 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable; + tcr_el1.T1SZ = 16; tcr_el1.SH0 = Aarch64::TCR_EL1::InnerShareable; tcr_el1.ORGN0 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable; tcr_el1.IRGN0 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable; + tcr_el1.T0SZ = 16; tcr_el1.TG1 = Aarch64::TCR_EL1::TG1GranuleSize::Size_4KB; tcr_el1.TG0 = Aarch64::TCR_EL1::TG0GranuleSize::Size_4KB;