From d6c620dc4f1b2f7221f3826b1a56cbe4b8642555 Mon Sep 17 00:00:00 2001 From: konrad Date: Sun, 22 Jan 2023 19:47:53 +0100 Subject: [PATCH] Kernel: Provide better types in MIDR register accessor for Aarch64 This avoids unnecessary and-masks during reading. --- Kernel/Arch/aarch64/Registers.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Kernel/Arch/aarch64/Registers.h b/Kernel/Arch/aarch64/Registers.h index d3e8c11b4f..dd96a6f82a 100644 --- a/Kernel/Arch/aarch64/Registers.h +++ b/Kernel/Arch/aarch64/Registers.h @@ -700,11 +700,11 @@ static_assert(sizeof(SCTLR_EL1) == 8); // https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/MIDR-EL1--Main-ID-Register?lang=en // MIDR_EL1, Main ID Register struct alignas(u64) MIDR_EL1 { - int Revision : 4; - int PartNum : 12; - int Architecture : 4; - int Variant : 4; - int Implementer : 8; + u8 Revision : 4; + u16 PartNum : 12; + u8 Architecture : 4; + u8 Variant : 4; + u8 Implementer : 8; int : 32; static inline MIDR_EL1 read()