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https://github.com/RGBCube/serenity
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UserspaceEmulator: Implement the OR family of instructions
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cb2e36dde7
commit
d79f15e219
1 changed files with 32 additions and 14 deletions
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@ -220,6 +220,37 @@ static typename TypeDoubler<Destination>::type op_xor(SoftCPU& cpu, const Destin
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return result;
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}
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template<typename Destination, typename Source>
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static typename TypeDoubler<Destination>::type op_or(SoftCPU& cpu, const Destination& dest, const Source& src)
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{
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Destination result = 0;
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u32 new_flags = 0;
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if constexpr (sizeof(Destination) == 4) {
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asm volatile("orl %%ecx, %%eax\n"
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: "=a"(result)
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: "a"(dest), "c"((u32)src));
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} else if constexpr (sizeof(Destination) == 2) {
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asm volatile("or %%cx, %%ax\n"
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: "=a"(result)
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: "a"(dest), "c"((u16)src));
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} else if constexpr (sizeof(Destination) == 1) {
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asm volatile("orb %%cl, %%al\n"
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: "=a"(result)
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: "a"(dest), "c"((u8)src));
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} else {
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ASSERT_NOT_REACHED();
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}
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asm volatile(
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"pushf\n"
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"pop %%ebx"
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: "=b"(new_flags));
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cpu.set_flags_oszpc(new_flags);
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return result;
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}
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template<typename Destination, typename Source>
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static typename TypeDoubler<Destination>::type op_sub(SoftCPU& cpu, const Destination& dest, const Source& src)
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{
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@ -864,20 +895,6 @@ void SoftCPU::NOP(const X86::Instruction&) { TODO(); }
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void SoftCPU::NOT_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::NOT_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::NOT_RM8(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_AL_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_AX_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_EAX_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_RM16_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_RM32_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_RM8_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_RM8_reg8(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_reg16_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::OR_reg8_RM8(const X86::Instruction&) { TODO(); }
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void SoftCPU::OUTSB(const X86::Instruction&) { TODO(); }
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void SoftCPU::OUTSD(const X86::Instruction&) { TODO(); }
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void SoftCPU::OUTSW(const X86::Instruction&) { TODO(); }
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@ -1213,6 +1230,7 @@ void SoftCPU::XLAT(const X86::Instruction&) { TODO(); }
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void SoftCPU::mnemonic##_reg8_RM8(const X86::Instruction& insn) { generic_reg8_RM8<update_dest>(op<u8, u8>, insn); }
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DEFINE_GENERIC_INSN_HANDLERS(XOR, op_xor, true)
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DEFINE_GENERIC_INSN_HANDLERS(OR, op_or, true)
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DEFINE_GENERIC_INSN_HANDLERS(ADD, op_add, true)
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DEFINE_GENERIC_INSN_HANDLERS(SUB, op_sub, true)
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DEFINE_GENERIC_INSN_HANDLERS(AND, op_and, true)
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