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Kernel: Add ID_AA64ISAR0_EL1, Instruction Set Attribute Register 0
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/*
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* Copyright (c) 2021, James Mintram <me@jamesrm.com>
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* Copyright (c) 2021, Marcin Undak <mcinek@gmail.com>
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* Copyright (c) 2022, Konrad <konrad@serenityos.org>
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* Copyright (c) 2022, the SerenityOS developers.
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*
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* SPDX-License-Identifier: BSD-2-Clause
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namespace Kernel::Aarch64 {
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// https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0?lang=en
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// ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0
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struct alignas(u64) ID_AA64ISAR0_EL1 {
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int : 4;
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int AES : 4;
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int SHA1 : 4;
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int SHA2 : 4;
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int CRC32 : 4;
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int Atomic : 4;
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int TME : 4;
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int RDM : 4;
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int SHA3 : 4;
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int SM3 : 4;
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int SM4 : 4;
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int DP : 4;
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int FHM : 4;
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int TS : 4;
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int TLB : 4;
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int RNDR : 4;
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static inline ID_AA64ISAR0_EL1 read()
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{
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ID_AA64ISAR0_EL1 feature_register;
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asm("mrs %[value], ID_AA64ISAR0_EL1"
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: [value] "=r"(feature_register));
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return feature_register;
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}
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};
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static_assert(sizeof(ID_AA64ISAR0_EL1) == 8);
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/ID-AA64MMFR0-EL1--AArch64-Memory-Model-Feature-Register-0
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// Memory Model Feature Register 0
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struct alignas(u64) ID_AA64MMFR0_EL1 {
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