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Kernel: Apply changes to use LibBareMetal definitions

This commit is contained in:
Liav A 2020-02-09 16:47:15 +02:00 committed by Andreas Kling
parent 7c507c27bf
commit e559af2008
43 changed files with 84 additions and 892 deletions

View file

@ -26,10 +26,10 @@
#include <AK/Assertions.h>
#include <AK/Types.h>
#include <Kernel/Arch/i386/CPU.h>
#include <Kernel/Arch/i386/APIC.h>
#include <Kernel/IO.h>
#include <Kernel/Arch/i386/CPU.h>
#include <Kernel/VM/MemoryManager.h>
#include <LibBareMetal/IO.h>
#define IRQ_APIC_SPURIOUS 0x1f
@ -56,12 +56,11 @@ asm(
namespace APIC {
class ICRReg
{
u32 m_reg{0};
class ICRReg {
u32 m_reg { 0 };
public:
enum DeliveryMode
{
enum DeliveryMode {
Fixed = 0x0,
LowPriority = 0x1,
SMI = 0x2,
@ -69,31 +68,27 @@ public:
INIT = 0x5,
StartUp = 0x6,
};
enum DestinationMode
{
enum DestinationMode {
Physical = 0x0,
Logical = 0x0,
};
enum Level
{
enum Level {
DeAssert = 0x0,
Assert = 0x1
};
enum class TriggerMode
{
enum class TriggerMode {
Edge = 0x0,
Level = 0x1,
};
enum DestinationShorthand
{
enum DestinationShorthand {
NoShorthand = 0x0,
Self = 0x1,
AllIncludingSelf = 0x2,
AllExcludingSelf = 0x3,
};
ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destination):
m_reg(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination << 18))
ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destination)
: m_reg(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination << 18))
{
}
@ -180,38 +175,40 @@ bool init()
void enable(u32 cpu)
{
kprintf("Enabling local APIC for cpu #%u\n", cpu);
// set spurious interrupt vector
apic_write(APIC_REG_SIV, apic_read(APIC_REG_SIV) | 0x100);
// local destination mode (flat mode)
apic_write(APIC_REG_DF, 0xf000000);
// set destination id (note that this limits it to 8 cpus)
apic_write(APIC_REG_LD, (1 << cpu) << 24);
register_interrupt_handler(IRQ_APIC_SPURIOUS, apic_spurious_interrupt_entry);
apic_write(APIC_REG_LVT_TIMER, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
apic_write(APIC_REG_LVT_THERMAL, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
apic_write(APIC_REG_LVT_PERFORMANCE_COUNTER, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
apic_write(APIC_REG_LVT_LINT0, APIC_LVT(0x1f, 7) | APIC_LVT_MASKED);
apic_write(APIC_REG_LVT_LINT1, APIC_LVT(0xff, 4) | APIC_LVT_TRIGGER_LEVEL); // nmi
apic_write(APIC_REG_LVT_ERR, APIC_LVT(0xe3, 0) | APIC_LVT_MASKED);
if (cpu == 0) {
static volatile u32 foo = 0;
// INIT
apic_write_icr(ICRReg(0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
for (foo = 0; foo < 0x800000; foo++); // TODO: 10 millisecond delay
for (foo = 0; foo < 0x800000; foo++)
; // TODO: 10 millisecond delay
for (int i = 0; i < 2; i++) {
// SIPI
apic_write_icr(ICRReg(0x08, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf)); // start execution at P8000
for (foo = 0; foo < 0x80000; foo++); // TODO: 200 microsecond delay
for (foo = 0; foo < 0x80000; foo++)
; // TODO: 200 microsecond delay
}
}
}

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@ -30,7 +30,7 @@
#include <AK/Noncopyable.h>
#include <Kernel/VM/PhysicalAddress.h>
#include <Kernel/VM/VirtualAddress.h>
#include <Kernel/kstdio.h>
#include <LibBareMetal/Output/kstdio.h>
#define PAGE_SIZE 4096
#define PAGE_MASK ((uintptr_t)0xfffff000u)

View file

@ -28,7 +28,7 @@
#include <AK/Types.h>
#include <Kernel/Arch/i386/CPU.h>
#include <Kernel/Arch/i386/PIC.h>
#include <Kernel/IO.h>
#include <LibBareMetal/IO.h>
// The slave 8259 is connected to the master's IRQ2 line.
// This is really only to enhance clarity.
@ -137,4 +137,3 @@ u16 get_irr()
}
}

View file

@ -27,8 +27,8 @@
#include <Kernel/Arch/i386/CPU.h>
#include <Kernel/Arch/i386/PIC.h>
#include <Kernel/Arch/i386/PIT.h>
#include <Kernel/IO.h>
#include <Kernel/Scheduler.h>
#include <LibBareMetal/IO.h>
#define IRQ_TIMER 0