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https://github.com/RGBCube/serenity
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Kernel: Apply changes to use LibBareMetal definitions
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7c507c27bf
commit
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43 changed files with 84 additions and 892 deletions
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@ -26,10 +26,10 @@
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#include <AK/Assertions.h>
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#include <AK/Types.h>
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#include <Kernel/Arch/i386/CPU.h>
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#include <Kernel/Arch/i386/APIC.h>
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#include <Kernel/IO.h>
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#include <Kernel/Arch/i386/CPU.h>
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#include <Kernel/VM/MemoryManager.h>
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#include <LibBareMetal/IO.h>
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#define IRQ_APIC_SPURIOUS 0x1f
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@ -56,12 +56,11 @@ asm(
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namespace APIC {
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class ICRReg
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{
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u32 m_reg{0};
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class ICRReg {
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u32 m_reg { 0 };
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public:
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enum DeliveryMode
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{
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enum DeliveryMode {
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Fixed = 0x0,
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LowPriority = 0x1,
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SMI = 0x2,
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@ -69,31 +68,27 @@ public:
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INIT = 0x5,
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StartUp = 0x6,
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};
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enum DestinationMode
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{
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enum DestinationMode {
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Physical = 0x0,
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Logical = 0x0,
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};
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enum Level
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{
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enum Level {
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DeAssert = 0x0,
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Assert = 0x1
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};
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enum class TriggerMode
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{
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enum class TriggerMode {
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Edge = 0x0,
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Level = 0x1,
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};
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enum DestinationShorthand
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{
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enum DestinationShorthand {
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NoShorthand = 0x0,
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Self = 0x1,
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AllIncludingSelf = 0x2,
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AllExcludingSelf = 0x3,
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};
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ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destination):
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m_reg(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination << 18))
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ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destination)
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: m_reg(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination << 18))
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{
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}
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@ -180,38 +175,40 @@ bool init()
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void enable(u32 cpu)
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{
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kprintf("Enabling local APIC for cpu #%u\n", cpu);
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// set spurious interrupt vector
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apic_write(APIC_REG_SIV, apic_read(APIC_REG_SIV) | 0x100);
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// local destination mode (flat mode)
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apic_write(APIC_REG_DF, 0xf000000);
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// set destination id (note that this limits it to 8 cpus)
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apic_write(APIC_REG_LD, (1 << cpu) << 24);
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register_interrupt_handler(IRQ_APIC_SPURIOUS, apic_spurious_interrupt_entry);
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apic_write(APIC_REG_LVT_TIMER, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
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apic_write(APIC_REG_LVT_THERMAL, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
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apic_write(APIC_REG_LVT_PERFORMANCE_COUNTER, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
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apic_write(APIC_REG_LVT_LINT0, APIC_LVT(0x1f, 7) | APIC_LVT_MASKED);
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apic_write(APIC_REG_LVT_LINT1, APIC_LVT(0xff, 4) | APIC_LVT_TRIGGER_LEVEL); // nmi
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apic_write(APIC_REG_LVT_ERR, APIC_LVT(0xe3, 0) | APIC_LVT_MASKED);
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if (cpu == 0) {
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static volatile u32 foo = 0;
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// INIT
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apic_write_icr(ICRReg(0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
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for (foo = 0; foo < 0x800000; foo++); // TODO: 10 millisecond delay
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for (foo = 0; foo < 0x800000; foo++)
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; // TODO: 10 millisecond delay
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for (int i = 0; i < 2; i++) {
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// SIPI
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apic_write_icr(ICRReg(0x08, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf)); // start execution at P8000
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for (foo = 0; foo < 0x80000; foo++); // TODO: 200 microsecond delay
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for (foo = 0; foo < 0x80000; foo++)
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; // TODO: 200 microsecond delay
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}
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}
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}
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@ -30,7 +30,7 @@
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#include <AK/Noncopyable.h>
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#include <Kernel/VM/PhysicalAddress.h>
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#include <Kernel/VM/VirtualAddress.h>
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#include <Kernel/kstdio.h>
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#include <LibBareMetal/Output/kstdio.h>
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#define PAGE_SIZE 4096
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#define PAGE_MASK ((uintptr_t)0xfffff000u)
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@ -28,7 +28,7 @@
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#include <AK/Types.h>
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#include <Kernel/Arch/i386/CPU.h>
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#include <Kernel/Arch/i386/PIC.h>
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#include <Kernel/IO.h>
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#include <LibBareMetal/IO.h>
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// The slave 8259 is connected to the master's IRQ2 line.
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// This is really only to enhance clarity.
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@ -137,4 +137,3 @@ u16 get_irr()
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}
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}
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@ -27,8 +27,8 @@
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#include <Kernel/Arch/i386/CPU.h>
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#include <Kernel/Arch/i386/PIC.h>
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#include <Kernel/Arch/i386/PIT.h>
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#include <Kernel/IO.h>
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#include <Kernel/Scheduler.h>
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#include <LibBareMetal/IO.h>
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#define IRQ_TIMER 0
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