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https://github.com/RGBCube/serenity
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Kernel/Net: Implement support for RTL8168C
Please be aware that I only have NIC with chip version 6 so this is the only one that I have tested. Rest was implemented via looking at Linux rtl8169 driver. Also thanks to IdanHo for some initial work.
This commit is contained in:
mrkubax10
Andrew Kaster
parent
15d6b3017a
commit
eb0d56a4ed
2 changed files with 179 additions and 11 deletions
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@ -38,6 +38,8 @@ namespace Kernel {
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#define REG_CSI_DATA 0x64
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#define REG_CSI_ADDR 0x68
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#define REG_PHYSTATUS 0x6C
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#define REG_MACDBG 0x6D
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#define REG_GPIO 0x6E
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#define REG_PMCH 0x6F
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#define REG_ERI_DATA 0x70
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#define REG_ERI_ADDR 0x74
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@ -46,6 +48,7 @@ namespace Kernel {
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#define REG_OCP_ADDR 0xB4
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#define REG_GPHY_OCP 0xB8
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#define REG_DLLPR 0xD0
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#define REG_DBG 0xD1
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#define REG_MCU 0xD3
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#define REG_RMS 0xDA
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#define REG_CPLUS_COMMAND 0xE0
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@ -61,6 +64,7 @@ namespace Kernel {
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#define COMMAND_TX_ENABLE 0x4
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#define COMMAND_RX_ENABLE 0x8
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#define COMMAND_RESET 0x10
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#define COMMAND_STOP 0x80
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#define CPLUS_COMMAND_VERIFY_CHECKSUM 0x20
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#define CPLUS_COMMAND_VLAN_STRIP 0x40
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@ -104,6 +108,8 @@ namespace Kernel {
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#define RXCFG_MULTI_ENABLE 0x4000
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#define RXCFG_128INT_ENABLE 0x8000
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#define CFG1_SPEED_DOWN 0x10
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#define CFG2_CLOCK_REQUEST_ENABLE 0x80
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#define CFG3_BEACON_ENABLE 0x1
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@ -180,6 +186,11 @@ namespace Kernel {
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#define PHYSTATUS_100M 0x08
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#define PHYSTATUS_10M 0x04
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#define GPIO_ENABLE 0x1
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#define DBG_FIX_NAK_2 0x8
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#define DBG_FIX_NAK_1 0x10
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#define TX_BUFFER_SIZE 0x1FF8
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#define RX_BUFFER_SIZE 0x1FF8 // FIXME: this should be increased (0x3FFF)
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@ -206,10 +217,10 @@ bool RTL8168NetworkAdapter::determine_supported_version() const
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case ChipVersion::Version1:
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case ChipVersion::Version2:
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case ChipVersion::Version3:
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return true;
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case ChipVersion::Version4:
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case ChipVersion::Version5:
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case ChipVersion::Version6:
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return true;
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case ChipVersion::Version7:
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case ChipVersion::Version8:
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case ChipVersion::Version9:
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@ -325,12 +336,14 @@ UNMAP_AFTER_INIT ErrorOr<void> RTL8168NetworkAdapter::initialize(Badge<Networkin
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Processor::wait_check();
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}
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// software reset
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reset();
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// clear interrupts
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out16(REG_ISR, 0xffff);
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pci_commit();
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// software reset
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reset();
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enable_bus_mastering(device_identifier());
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read_mac_address();
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@ -362,6 +375,17 @@ void RTL8168NetworkAdapter::startup()
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// version specific phy configuration
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configure_phy();
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pci_commit();
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// disable interrupts
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out16(REG_IMR, 0);
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out16(REG_ISR, 0xffff);
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pci_commit();
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// send stop command
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out8(REG_COMMAND, COMMAND_STOP);
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reset();
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// software reset phy
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phy_out(PHY_REG_BMCR, phy_in(PHY_REG_BMCR) | BMCR_RESET);
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@ -375,6 +399,13 @@ void RTL8168NetworkAdapter::startup()
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out16(REG_CPLUS_COMMAND, cplus_command);
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in16(REG_CPLUS_COMMAND); // C+ Command barrier
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if (m_version == ChipVersion::Version5 || m_version == ChipVersion::Version6) {
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if (in8(REG_MACDBG) & 0x80)
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out8(REG_GPIO, in8(REG_GPIO) | GPIO_ENABLE);
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else
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out8(REG_GPIO, in8(REG_GPIO) & ~GPIO_ENABLE);
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}
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// power up phy
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if (m_version >= ChipVersion::Version9 && m_version <= ChipVersion::Version15) {
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out8(REG_PMCH, in8(REG_PMCH) | 0x80);
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@ -393,6 +424,7 @@ void RTL8168NetworkAdapter::startup()
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}
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phy_out(PHY_REG_BMCR, BMCR_AUTO_NEGOTIATE); // send known good phy write (acts as a phy barrier)
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start_hardware();
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pci_commit();
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// re-enable interrupts
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auto enabled_interrupts = INT_RXOK | INT_RXERR | INT_TXOK | INT_TXERR | INT_RX_OVERFLOW | INT_LINK_CHANGE | INT_SYS_ERR;
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@ -401,6 +433,7 @@ void RTL8168NetworkAdapter::startup()
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enabled_interrupts &= ~INT_RX_OVERFLOW;
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}
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out16(REG_IMR, enabled_interrupts);
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pci_commit();
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// update link status
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m_link_up = (in8(REG_PHYSTATUS) & PHY_LINK_STATUS) != 0;
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@ -420,11 +453,14 @@ void RTL8168NetworkAdapter::configure_phy()
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return;
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}
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case ChipVersion::Version4:
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TODO();
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configure_phy_c_1();
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return;
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case ChipVersion::Version5:
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TODO();
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configure_phy_c_2();
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return;
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case ChipVersion::Version6:
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TODO();
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configure_phy_c_3();
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return;
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case ChipVersion::Version7:
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TODO();
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case ChipVersion::Version8:
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@ -510,6 +546,79 @@ void RTL8168NetworkAdapter::configure_phy_b_2()
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phy_out_batch(phy_registers);
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}
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void RTL8168NetworkAdapter::configure_phy_c_1()
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{
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static constexpr auto phy_registers = to_array<PhyRegister>({
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{ 0x1f, 0x0001 },
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{ 0x12, 0x2300 },
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{ 0x1f, 0x0002 },
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{ 0x00, 0x88d4 },
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{ 0x01, 0x82b1 },
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{ 0x03, 0x7002 },
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{ 0x08, 0x9e30 },
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{ 0x09, 0x01f0 },
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{ 0x0a, 0x5500 },
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{ 0x0c, 0x00c8 },
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{ 0x1f, 0x0003 },
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{ 0x12, 0xc096 },
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{ 0x16, 0x000a },
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{ 0x1f, 0x0000 },
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{ 0x1f, 0x0000 },
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{ 0x09, 0x2000 },
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{ 0x09, 0x0000 },
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});
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phy_out_batch(phy_registers);
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phy_update(0x14, 1 << 5, 0);
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phy_update(0x0d, 1 << 5, 0);
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}
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void RTL8168NetworkAdapter::configure_phy_c_2()
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{
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static constexpr auto phy_registers = to_array<PhyRegister>({
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{ 0x1f, 0x0001 },
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{ 0x12, 0x2300 },
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{ 0x03, 0x802f },
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{ 0x02, 0x4f02 },
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{ 0x01, 0x0409 },
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{ 0x00, 0xf099 },
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{ 0x04, 0x9800 },
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{ 0x04, 0x9000 },
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{ 0x1d, 0x3d98 },
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{ 0x1f, 0x0002 },
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{ 0x0c, 0x7eb8 },
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{ 0x06, 0x0761 },
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{ 0x1f, 0x0003 },
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{ 0x16, 0x0f0a },
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{ 0x1f, 0x0000 },
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});
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phy_out_batch(phy_registers);
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phy_update(0x16, 0x1, 0);
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phy_update(0x14, 1 << 5, 0);
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phy_update(0x0d, 1 << 5, 0);
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}
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void RTL8168NetworkAdapter::configure_phy_c_3()
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{
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static constexpr auto phy_registers = to_array<PhyRegister>({
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{ 0x1f, 0x0001 },
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{ 0x12, 0x2300 },
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{ 0x1d, 0x3d98 },
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{ 0x1f, 0x0002 },
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{ 0x0c, 0x7eb8 },
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{ 0x06, 0x5461 },
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{ 0x1f, 0x0003 },
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{ 0x16, 0x0f0a },
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{ 0x1f, 0x0000 },
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});
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phy_out_batch(phy_registers);
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phy_update(0x16, 0x1, 0);
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phy_update(0x14, 1 << 5, 0);
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phy_update(0x0d, 1 << 5, 0);
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}
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void RTL8168NetworkAdapter::configure_phy_e_2()
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{
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// FIXME: linux's driver writes a firmware blob to the device at this point, is this needed?
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@ -794,7 +903,6 @@ void RTL8168NetworkAdapter::rar_exgmac_set()
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void RTL8168NetworkAdapter::start_hardware()
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{
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// unlock config registers
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out8(REG_CFG9346, CFG9346_UNLOCK);
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@ -832,6 +940,7 @@ void RTL8168NetworkAdapter::start_hardware()
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// enable rx/tx
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out8(REG_COMMAND, COMMAND_RX_ENABLE | COMMAND_TX_ENABLE);
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pci_commit();
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// turn on all multicast
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out32(REG_MAR0, 0xFFFFFFFF);
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@ -855,11 +964,14 @@ void RTL8168NetworkAdapter::hardware_quirks()
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hardware_quirks_b_2();
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return;
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case ChipVersion::Version4:
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TODO();
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hardware_quirks_c_1();
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return;
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case ChipVersion::Version5:
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TODO();
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hardware_quirks_c_2();
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return;
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case ChipVersion::Version6:
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TODO();
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hardware_quirks_c_3();
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return;
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case ChipVersion::Version7:
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TODO();
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case ChipVersion::Version8:
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@ -933,6 +1045,49 @@ void RTL8168NetworkAdapter::hardware_quirks_b_2()
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out8(REG_CONFIG4, in8(REG_CONFIG4) & ~1);
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}
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void RTL8168NetworkAdapter::hardware_quirks_c_1()
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{
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csi_enable(CSI_ACCESS_2);
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out8(REG_DBG, 0x06 | DBG_FIX_NAK_1 | DBG_FIX_NAK_2);
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static constexpr auto ephy_info = to_array<EPhyUpdate>({
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{ 0x02, 0x0800, 0x1000 },
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{ 0x03, 0, 0x0002 },
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{ 0x06, 0x0080, 0x0000 },
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});
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extended_phy_initialize(ephy_info);
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out8(REG_CONFIG1, in8(REG_CONFIG1) | CFG1_SPEED_DOWN);
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out8(REG_CONFIG3, in8(REG_CONFIG3) & ~CFG3_BEACON_ENABLE);
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}
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void RTL8168NetworkAdapter::hardware_quirks_c_2()
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{
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csi_enable(CSI_ACCESS_2);
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static constexpr auto ephy_info = to_array<EPhyUpdate>({
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{ 0x01, 0, 0x1 },
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{ 0x03, 0x0400, 0x0020 },
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});
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extended_phy_initialize(ephy_info);
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out8(REG_CONFIG1, in8(REG_CONFIG1) | CFG1_SPEED_DOWN);
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out8(REG_CONFIG3, in8(REG_CONFIG3) | CFG3_BEACON_ENABLE);
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// FIXME: Disable PCIe clock request
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}
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void RTL8168NetworkAdapter::hardware_quirks_c_3()
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{
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csi_enable(CSI_ACCESS_2);
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out8(REG_CONFIG1, in8(REG_CONFIG1) | CFG1_SPEED_DOWN);
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out8(REG_CONFIG3, in8(REG_CONFIG3) & ~CFG3_BEACON_ENABLE);
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// FIXME: Disable PCIe clock request
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}
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void RTL8168NetworkAdapter::hardware_quirks_e_2()
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{
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static constexpr auto ephy_info = to_array<EPhyUpdate>({
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@ -1186,6 +1341,12 @@ void RTL8168NetworkAdapter::reset()
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Processor::wait_check();
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}
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void RTL8168NetworkAdapter::pci_commit()
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{
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// read any register to commit previous PCI write
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in8(REG_COMMAND);
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}
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UNMAP_AFTER_INIT void RTL8168NetworkAdapter::read_mac_address()
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{
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MACAddress mac {};
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@ -129,6 +129,7 @@ private:
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StringView possible_device_name();
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void reset();
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void pci_commit();
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void read_mac_address();
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void set_phy_speed();
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void start_hardware();
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@ -137,6 +138,9 @@ private:
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void configure_phy();
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void configure_phy_b_1();
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void configure_phy_b_2();
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void configure_phy_c_1();
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void configure_phy_c_2();
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void configure_phy_c_3();
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void configure_phy_e_2();
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void configure_phy_h_1();
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void configure_phy_h_2();
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@ -146,6 +150,9 @@ private:
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void hardware_quirks();
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void hardware_quirks_b_1();
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void hardware_quirks_b_2();
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void hardware_quirks_c_1();
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void hardware_quirks_c_2();
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void hardware_quirks_c_3();
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void hardware_quirks_e_2();
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void hardware_quirks_h();
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