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Kernel: Make Aarch64 register variables bit more descriptive

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This commit is contained in:
Marcin Undak 2021-10-14 11:43:25 -04:00 • committed by Linus Groh
parent 2d9fa8146c
commit ebf810f9a6
1 changed files with 28 additions and 28 deletions
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56
Kernel/Prekernel/Arch/aarch64/init.cpp
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@ -64,85 +64,85 @@ void __stack_chk_fail()
static void set_up_el1_mode()
{
Kernel::Aarch64_SCTLR_EL1 sctlr_el1 = {};
Kernel::Aarch64_SCTLR_EL1 system_control_register_el1 = {};
// Those bits are reserved on ARMv8.0
sctlr_el1.LSMAOE = 1;
sctlr_el1.nTLSMD = 1;
sctlr_el1.SPAN = 1;
sctlr_el1.IESB = 1;
system_control_register_el1.LSMAOE = 1;
system_control_register_el1.nTLSMD = 1;
system_control_register_el1.SPAN = 1;
system_control_register_el1.IESB = 1;
// Don't trap access to CTR_EL0
sctlr_el1.UCT = 1;
system_control_register_el1.UCT = 1;
// Don't trap WFE instructions
sctlr_el1.nTWE = 1;
system_control_register_el1.nTWE = 1;
// Don't trap WFI instructions
sctlr_el1.nTWI = 1;
system_control_register_el1.nTWI = 1;
// Don't trap DC ZVA instructions
sctlr_el1.DZE = 1;
system_control_register_el1.DZE = 1;
// Don't trap access to DAIF (debugging) flags of EFLAGS register
sctlr_el1.UMA = 1;
system_control_register_el1.UMA = 1;
// Enable stack access alignment check for EL0
sctlr_el1.SA0 = 1;
system_control_register_el1.SA0 = 1;
// Enable stack access alignment check for EL1
sctlr_el1.SA = 1;
system_control_register_el1.SA = 1;
// Enable memory access alignment check
sctlr_el1.A = 1;
system_control_register_el1.A = 1;
// Set the register
asm("msr sctlr_el1, %[value]" ::[value] "r"(sctlr_el1));
asm("msr sctlr_el1, %[value]" ::[value] "r"(system_control_register_el1));
}
static void set_up_el2_mode()
{
Kernel::Aarch64_HCR_EL2 hcr_el2 = {};
Kernel::Aarch64_HCR_EL2 hypervisor_configuration_register_el2 = {};
// EL1 to use 64-bit mode
hcr_el2.RW = 1;
hypervisor_configuration_register_el2.RW = 1;
// Set the register
asm("msr hcr_el2, %[value]" ::[value] "r"(hcr_el2));
asm("msr hcr_el2, %[value]" ::[value] "r"(hypervisor_configuration_register_el2));
}
static void set_up_el3_mode()
{
Kernel::Aarch64_SCR_EL3 scr_el3 = {};
Kernel::Aarch64_SCR_EL3 secure_configuration_register_el3 = {};
// Don't trap access to Counter-timer Physical Secure registers
scr_el3.ST = 1;
secure_configuration_register_el3.ST = 1;
// Lower level to use Aarch64
scr_el3.RW = 1;
secure_configuration_register_el3.RW = 1;
// Enable Hypervisor instructions at all levels
scr_el3.HCE = 1;
secure_configuration_register_el3.HCE = 1;
// Set the register
asm("msr scr_el3, %[value]" ::[value] "r"(scr_el3));
asm("msr scr_el3, %[value]" ::[value] "r"(secure_configuration_register_el3));
}
[[noreturn]] static void switch_to_el1()
{
// Processor state to set when returned from this function (in new EL1 world)
Kernel::Aarch64_SPSR_EL3 spsr_el3 = {};
Kernel::Aarch64_SPSR_EL3 saved_program_status_register_el3 = {};
// Mask (disable) all interrupts
spsr_el3.A = 1;
spsr_el3.I = 1;
spsr_el3.F = 1;
saved_program_status_register_el3.A = 1;
saved_program_status_register_el3.I = 1;
saved_program_status_register_el3.F = 1;
// Indicate EL1 as exception origin mode (so we go back there)
spsr_el3.M = Kernel::Aarch64_SPSR_EL3::Mode::EL1h;
saved_program_status_register_el3.M = Kernel::Aarch64_SPSR_EL3::Mode::EL1h;
// Set the register
asm("msr spsr_el3, %[value]" ::[value] "r"(spsr_el3));
asm("msr spsr_el3, %[value]" ::[value] "r"(saved_program_status_register_el3));
// This will jump into os_start() below, but in EL1
return_from_el3();