diff --git a/Kernel/Arch/PageFault.h b/Kernel/Arch/PageFault.h
index 27ad0eb49d..85f8f8f8ac 100644
--- a/Kernel/Arch/PageFault.h
+++ b/Kernel/Arch/PageFault.h
@@ -78,6 +78,8 @@ public:
     void set_mode(ExecutionMode execution_mode) { m_execution_mode = execution_mode; }
     ExecutionMode mode() const { return m_execution_mode; }
 
+    void set_instruction_fetch(bool b) { m_is_instruction_fetch = b; }
+
     bool is_not_present() const { return m_type == Type::PageNotPresent; }
     bool is_protection_violation() const { return m_type == Type::ProtectionViolation; }
     bool is_read() const { return m_access == Access::Read; }
diff --git a/Kernel/Arch/aarch64/Interrupts.cpp b/Kernel/Arch/aarch64/Interrupts.cpp
index d5560b307f..3cddb3ee9c 100644
--- a/Kernel/Arch/aarch64/Interrupts.cpp
+++ b/Kernel/Arch/aarch64/Interrupts.cpp
@@ -73,6 +73,9 @@ static PageFault page_fault_from_exception_syndrome_register(VirtualAddress faul
     // FIXME: Set correct mode
     fault.set_mode(ExecutionMode::Kernel);
 
+    if (Aarch64::exception_class_is_instruction_abort(esr_el1.EC))
+        fault.set_instruction_fetch(true);
+
     return fault;
 }
 
@@ -92,7 +95,7 @@ extern "C" void exception_common(Kernel::TrapFrame* trap_frame)
         dump_exception_syndrome_register(esr_el1);
     }
 
-    if (Aarch64::exception_class_is_data_abort(esr_el1.EC)) {
+    if (Aarch64::exception_class_is_data_abort(esr_el1.EC) || Aarch64::exception_class_is_instruction_abort(esr_el1.EC)) {
         auto page_fault = page_fault_from_exception_syndrome_register(VirtualAddress(fault_address), esr_el1);
         page_fault.handle(*trap_frame->regs);
     } else {
diff --git a/Kernel/Arch/aarch64/Registers.h b/Kernel/Arch/aarch64/Registers.h
index 08c291c5fa..5eac1c93e7 100644
--- a/Kernel/Arch/aarch64/Registers.h
+++ b/Kernel/Arch/aarch64/Registers.h
@@ -1162,6 +1162,11 @@ static inline bool exception_class_is_data_abort(u8 exception_class)
     return exception_class == 0x24 || exception_class == 0x25;
 }
 
+static inline bool exception_class_is_instruction_abort(u8 exception_class)
+{
+    return exception_class == 0x20 || exception_class == 0x21;
+}
+
 // D17.2.37 ESR_EL1, Exception Syndrome Register (EL1)
 // ISS encoding for an exception from a Data Abort
 // DFSC, bits [5:0]