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https://github.com/RGBCube/serenity
synced 2025-07-26 22:07:36 +00:00
LibX86: Use names closer to the spec for the Modrm
This gets rid of a lot of magic number shifts and ands.
This commit is contained in:
Hendiadyoin1
Andreas Kling
parent
68193c365f
commit
efa42c4d45
3 changed files with 58 additions and 53 deletions
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@ -1721,7 +1721,7 @@ void SoftCPU::FCMOVB(const X86::Instruction& insn)
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{
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VERIFY(insn.modrm().is_register());
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if (cf())
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fpu_set(0, fpu_get(insn.rm() & 7));
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fpu_set(0, fpu_get(insn.modrm().rm()));
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}
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void SoftCPU::FIMUL_RM32(const X86::Instruction& insn)
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@ -1736,7 +1736,7 @@ void SoftCPU::FCMOVE(const X86::Instruction& insn)
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{
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VERIFY(insn.modrm().is_register());
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if (zf())
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fpu_set(0, fpu_get(insn.rm() & 7));
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fpu_set(0, fpu_get(insn.modrm().rm()));
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}
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void SoftCPU::FICOM_RM32(const X86::Instruction&) { TODO_INSN(); }
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@ -1744,7 +1744,7 @@ void SoftCPU::FICOM_RM32(const X86::Instruction&) { TODO_INSN(); }
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void SoftCPU::FCMOVBE(const X86::Instruction& insn)
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{
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if (evaluate_condition(6))
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fpu_set(0, fpu_get(insn.rm() & 7));
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fpu_set(0, fpu_get(insn.modrm().rm()));
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}
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void SoftCPU::FICOMP_RM32(const X86::Instruction&) { TODO_INSN(); }
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@ -1832,7 +1832,7 @@ void SoftCPU::FIST_RM32(const X86::Instruction& insn)
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void SoftCPU::FCMOVNBE(const X86::Instruction& insn)
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{
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if (evaluate_condition(7))
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fpu_set(0, fpu_get(insn.rm() & 7));
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fpu_set(0, fpu_get(insn.modrm().rm()));
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}
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void SoftCPU::FISTP_RM32(const X86::Instruction& insn)
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@ -1869,7 +1869,7 @@ void SoftCPU::FLD_RM80(const X86::Instruction& insn)
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void SoftCPU::FUCOMI(const X86::Instruction& insn)
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{
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auto i = insn.rm() & 7;
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auto i = insn.modrm().rm();
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// FIXME: Unordered comparison checks.
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// FIXME: QNaN / exception handling.
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// FIXME: Set C0, C2, C3 in FPU status word.
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@ -1890,7 +1890,7 @@ void SoftCPU::FUCOMI(const X86::Instruction& insn)
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void SoftCPU::FCOMI(const X86::Instruction& insn)
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{
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auto i = insn.rm() & 7;
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auto i = insn.modrm().rm();
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// FIXME: QNaN / exception handling.
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// FIXME: Set C0, C2, C3 in FPU status word.
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set_zf(fpu_get(0) == fpu_get(i));
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@ -1037,7 +1037,7 @@ String MemoryOrRegisterReference::to_string_a16() const
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String base;
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bool hasDisplacement = false;
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switch (m_rm & 7) {
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switch (rm()) {
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case 0:
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base = "bx+si";
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break;
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@ -1060,16 +1060,16 @@ String MemoryOrRegisterReference::to_string_a16() const
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base = "bx";
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break;
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case 6:
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if ((m_rm & 0xc0) == 0)
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if (mod() == 0)
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base = String::formatted("{:#04x}", m_displacement16);
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else
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base = "bp";
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break;
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}
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switch (m_rm & 0xc0) {
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case 0x40:
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case 0x80:
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switch (mod()) {
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case 0b01:
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case 0b10:
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hasDisplacement = true;
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}
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@ -1178,16 +1178,16 @@ String MemoryOrRegisterReference::to_string_a32() const
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return register_name(static_cast<RegisterIndex32>(m_register_index));
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bool has_displacement = false;
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switch (m_rm & 0xc0) {
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case 0x40:
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case 0x80:
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switch (mod()) {
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case 0b01:
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case 0b10:
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has_displacement = true;
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}
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if (m_has_sib && (m_sib & 7) == 5)
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has_displacement = true;
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String base;
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switch (m_rm & 7) {
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switch (rm()) {
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case 0:
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base = "eax";
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break;
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@ -1207,13 +1207,13 @@ String MemoryOrRegisterReference::to_string_a32() const
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base = "edi";
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break;
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case 5:
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if ((m_rm & 0xc0) == 0)
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if (mod() == 0)
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base = String::formatted("{:#08x}", m_displacement32);
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else
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base = "ebp";
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break;
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case 4:
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base = sib_to_string(m_rm, m_sib);
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base = sib_to_string(m_rm_byte, m_sib);
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break;
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}
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@ -1766,7 +1766,7 @@ void Instruction::to_string_internal(StringBuilder& builder, u32 origin, const S
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break;
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case OP_reg32_CR:
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append_mnemonic_space();
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builder.append(register_name(static_cast<RegisterIndex32>(rm() & 7)));
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builder.append(register_name(static_cast<RegisterIndex32>(modrm().rm())));
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append(", ");
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append_creg();
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break;
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@ -1774,11 +1774,11 @@ void Instruction::to_string_internal(StringBuilder& builder, u32 origin, const S
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append_mnemonic_space();
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append_creg();
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append(", ");
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builder.append(register_name(static_cast<RegisterIndex32>(rm() & 7)));
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builder.append(register_name(static_cast<RegisterIndex32>(modrm().rm())));
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break;
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case OP_reg32_DR:
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append_mnemonic_space();
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builder.append(register_name(static_cast<RegisterIndex32>(rm() & 7)));
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builder.append(register_name(static_cast<RegisterIndex32>(modrm().rm())));
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append(", ");
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append_dreg();
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break;
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@ -1786,7 +1786,7 @@ void Instruction::to_string_internal(StringBuilder& builder, u32 origin, const S
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append_mnemonic_space();
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append_dreg();
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append(", ");
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builder.append(register_name(static_cast<RegisterIndex32>(rm() & 7)));
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builder.append(register_name(static_cast<RegisterIndex32>(modrm().rm())));
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break;
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case OP_short_imm8:
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append_mnemonic_space();
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@ -374,6 +374,11 @@ public:
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RegisterIndex8 reg8() const { return static_cast<RegisterIndex8>(register_index()); }
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FpuRegisterIndex reg_fpu() const { return static_cast<FpuRegisterIndex>(register_index()); }
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// helpers to get the parts by name as in the spec
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u8 mod() const { return m_rm_byte >> 6; }
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u8 reg() const { return m_rm_byte >> 3 & 0b111; }
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u8 rm() const { return m_rm_byte & 0b111; }
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template<typename CPU, typename T>
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void write8(CPU&, const Instruction&, T);
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template<typename CPU, typename T>
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@ -429,7 +434,7 @@ private:
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u16 m_displacement16;
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};
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u8 m_rm { 0 };
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u8 m_rm_byte { 0 };
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u8 m_sib { 0 };
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u8 m_displacement_bytes { 0 };
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u8 m_register_index : 7 { 0x7f };
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@ -467,8 +472,8 @@ public:
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String mnemonic() const;
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u8 op() const { return m_op; }
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u8 rm() const { return m_modrm.m_rm; }
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u8 slash() const { return (rm() >> 3) & 7; }
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u8 modrm_byte() const { return m_modrm.m_rm_byte; }
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u8 slash() const { return (modrm_byte() >> 3) & 7; }
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u8 imm8() const { return m_imm1; }
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u16 imm16() const { return m_imm1; }
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@ -535,7 +540,7 @@ ALWAYS_INLINE LogicalAddress MemoryOrRegisterReference::resolve16(const CPU& cpu
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auto default_segment = SegmentRegister::DS;
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u16 offset = 0;
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switch (m_rm & 7) {
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switch (rm()) {
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case 0:
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offset = cpu.bx().value() + cpu.si().value() + m_displacement16;
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break;
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@ -557,7 +562,7 @@ ALWAYS_INLINE LogicalAddress MemoryOrRegisterReference::resolve16(const CPU& cpu
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offset = cpu.di().value() + m_displacement16;
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break;
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case 6:
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if ((m_rm & 0xc0) == 0)
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if (mod() == 0)
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offset = m_displacement16;
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else {
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default_segment = SegmentRegister::SS;
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@ -579,16 +584,16 @@ ALWAYS_INLINE LogicalAddress MemoryOrRegisterReference::resolve32(const CPU& cpu
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auto default_segment = SegmentRegister::DS;
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u32 offset = 0;
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switch (m_rm & 0x07) {
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switch (rm()) {
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case 0 ... 3:
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case 6 ... 7:
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offset = cpu.const_gpr32((RegisterIndex32)(m_rm & 0x07)).value() + m_displacement32;
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offset = cpu.const_gpr32((RegisterIndex32)(rm())).value() + m_displacement32;
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break;
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case 4:
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offset = evaluate_sib(cpu, default_segment);
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break;
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default: // 5
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if ((m_rm & 0xc0) == 0x00) {
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if (mod() == 0) {
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offset = m_displacement32;
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break;
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} else {
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@ -628,7 +633,7 @@ ALWAYS_INLINE u32 MemoryOrRegisterReference::evaluate_sib(const CPU& cpu, Segmen
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base += cpu.esp().value();
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break;
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default: // 5
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switch ((m_rm >> 6) & 3) {
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switch (mod()) {
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case 0:
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break;
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case 1:
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@ -846,7 +851,7 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
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if (m_descriptor->has_rm) {
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// Consume ModR/M (may include SIB and displacement.)
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m_modrm.decode(stream, m_a32);
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m_register_index = (m_modrm.m_rm >> 3) & 7;
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m_register_index = m_modrm.reg();
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} else {
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if (has_sub_op())
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m_register_index = m_sub_op & 7;
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@ -857,8 +862,8 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
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bool has_slash = m_descriptor->format == MultibyteWithSlash;
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if (has_slash) {
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m_descriptor = &m_descriptor->slashes[slash()];
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if ((rm() & 0xc0) == 0xc0 && m_descriptor->slashes)
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m_descriptor = &m_descriptor->slashes[rm() & 7];
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if ((modrm_byte() & 0xc0) == 0xc0 && m_descriptor->slashes)
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m_descriptor = &m_descriptor->slashes[modrm_byte() & 7];
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}
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if (!m_descriptor->mnemonic) {
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@ -924,7 +929,7 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
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template<typename InstructionStreamType>
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ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stream, bool a32)
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{
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m_rm = stream.read8();
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m_rm_byte = stream.read8();
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if (a32) {
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decode32(stream);
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@ -962,21 +967,21 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stre
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template<typename InstructionStreamType>
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ALWAYS_INLINE void MemoryOrRegisterReference::decode16(InstructionStreamType&)
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{
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switch (m_rm & 0xc0) {
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case 0:
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if ((m_rm & 0x07) == 6)
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switch (mod()) {
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case 0b00:
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if (rm() == 6)
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m_displacement_bytes = 2;
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else
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VERIFY(m_displacement_bytes == 0);
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break;
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case 0x40:
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case 0b01:
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m_displacement_bytes = 1;
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break;
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case 0x80:
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case 0b10:
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m_displacement_bytes = 2;
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break;
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case 0xc0:
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m_register_index = m_rm & 7;
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case 0b11:
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m_register_index = rm();
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break;
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}
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}
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@ -984,34 +989,34 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode16(InstructionStreamType&)
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template<typename InstructionStreamType>
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ALWAYS_INLINE void MemoryOrRegisterReference::decode32(InstructionStreamType& stream)
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{
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switch (m_rm & 0xc0) {
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case 0:
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if ((m_rm & 0x07) == 5)
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switch (mod()) {
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case 0b00:
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if (rm() == 5)
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m_displacement_bytes = 4;
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break;
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case 0x40:
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case 0b01:
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m_displacement_bytes = 1;
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break;
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case 0x80:
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case 0b10:
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m_displacement_bytes = 4;
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break;
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case 0xc0:
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m_register_index = m_rm & 7;
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case 0b11:
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m_register_index = rm();
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return;
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}
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m_has_sib = (m_rm & 0x07) == 4;
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m_has_sib = rm() == 4;
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if (m_has_sib) {
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m_sib = stream.read8();
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if ((m_sib & 0x07) == 5) {
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switch ((m_rm >> 6) & 0x03) {
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case 0:
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switch (mod()) {
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case 0b00:
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m_displacement_bytes = 4;
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break;
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case 1:
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case 0b01:
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m_displacement_bytes = 1;
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break;
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case 2:
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case 0b10:
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m_displacement_bytes = 4;
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break;
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default:
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