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LibX86: ALWAYS_INLINE some Instruction members

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This commit is contained in:
Andreas Kling 2020-07-13 13:46:22 +02:00
parent a83fe7f82d
commit f1bbc39148
2 changed files with 15 additions and 18 deletions
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8
Libraries/LibX86/Instruction.cpp
View file

@ -971,6 +971,8 @@ Instruction::Instruction(InstructionStream& stream, bool o32, bool a32)
if (m_imm1_bytes) if (m_imm1_bytes)
m_imm1 = stream.read(m_imm1_bytes); m_imm1 = stream.read(m_imm1_bytes);
m_handler = m_descriptor->handler;
#ifdef DISALLOW_INVALID_LOCK_PREFIX #ifdef DISALLOW_INVALID_LOCK_PREFIX
if (m_has_lock_prefix && !m_descriptor->lock_prefix_allowed) { if (m_has_lock_prefix && !m_descriptor->lock_prefix_allowed) {
fprintf(stderr, "Instruction not allowed with LOCK prefix, this will raise #UD\n"); fprintf(stderr, "Instruction not allowed with LOCK prefix, this will raise #UD\n");
@ -1906,10 +1908,4 @@ void MemoryOrRegisterReference::decode32(InstructionStream& stream)
} }
} }
InstructionHandler Instruction::handler() const
{
ASSERT(m_descriptor->handler);
return m_descriptor->handler;
}
} }

25
Libraries/LibX86/Instruction.h
View file

@ -219,7 +219,7 @@ public:
u32 read32(CPU&, const Instruction&); u32 read32(CPU&, const Instruction&);
template<typename CPU> template<typename CPU>
LogicalAddress resolve(const CPU& cpu, Optional<SegmentRegister> segment_prefix) ALWAYS_INLINE LogicalAddress resolve(const CPU& cpu, Optional<SegmentRegister> segment_prefix)
{ {
if (m_a32) if (m_a32)
return resolve32(cpu, segment_prefix); return resolve32(cpu, segment_prefix);
@ -274,13 +274,13 @@ public:
static Instruction from_stream(InstructionStream&, bool o32, bool a32); static Instruction from_stream(InstructionStream&, bool o32, bool a32);
~Instruction() { } ~Instruction() { }
MemoryOrRegisterReference& modrm() const ALWAYS_INLINE MemoryOrRegisterReference& modrm() const
{ {
ASSERT(has_rm()); ASSERT(has_rm());
return m_modrm; return m_modrm;
} }
InstructionHandler handler() const; ALWAYS_INLINE InstructionHandler handler() const { return m_handler; }
bool has_segment_prefix() const { return m_segment_prefix.has_value(); } bool has_segment_prefix() const { return m_segment_prefix.has_value(); }
Optional<SegmentRegister> segment_prefix() const { return m_segment_prefix; } Optional<SegmentRegister> segment_prefix() const { return m_segment_prefix; }
@ -393,10 +393,11 @@ private:
mutable MemoryOrRegisterReference m_modrm; mutable MemoryOrRegisterReference m_modrm;
InstructionDescriptor* m_descriptor { nullptr }; InstructionDescriptor* m_descriptor { nullptr };
InstructionHandler m_handler { nullptr };
}; };
template<typename CPU> template<typename CPU>
LogicalAddress MemoryOrRegisterReference::resolve16(const CPU& cpu, Optional<SegmentRegister> segment_prefix) ALWAYS_INLINE LogicalAddress MemoryOrRegisterReference::resolve16(const CPU& cpu, Optional<SegmentRegister> segment_prefix)
{ {
ASSERT(!m_a32); ASSERT(!m_a32);
@ -442,7 +443,7 @@ LogicalAddress MemoryOrRegisterReference::resolve16(const CPU& cpu, Optional<Seg
} }
template<typename CPU> template<typename CPU>
inline LogicalAddress MemoryOrRegisterReference::resolve32(const CPU& cpu, Optional<SegmentRegister> segment_prefix) ALWAYS_INLINE LogicalAddress MemoryOrRegisterReference::resolve32(const CPU& cpu, Optional<SegmentRegister> segment_prefix)
{ {
ASSERT(m_a32); ASSERT(m_a32);
@ -487,7 +488,7 @@ inline LogicalAddress MemoryOrRegisterReference::resolve32(const CPU& cpu, Optio
} }
template<typename CPU> template<typename CPU>
inline u32 MemoryOrRegisterReference::evaluate_sib(const CPU& cpu, SegmentRegister& default_segment) const ALWAYS_INLINE u32 MemoryOrRegisterReference::evaluate_sib(const CPU& cpu, SegmentRegister& default_segment) const
{ {
u32 scale = 0; u32 scale = 0;
switch (m_sib & 0xc0) { switch (m_sib & 0xc0) {
@ -576,7 +577,7 @@ inline u32 MemoryOrRegisterReference::evaluate_sib(const CPU& cpu, SegmentRegist
} }
template<typename CPU> template<typename CPU>
inline void MemoryOrRegisterReference::write8(CPU& cpu, const Instruction& insn, u8 value) ALWAYS_INLINE void MemoryOrRegisterReference::write8(CPU& cpu, const Instruction& insn, u8 value)
{ {
if (is_register()) { if (is_register()) {
cpu.gpr8(reg8()) = value; cpu.gpr8(reg8()) = value;
@ -588,7 +589,7 @@ inline void MemoryOrRegisterReference::write8(CPU& cpu, const Instruction& insn,
} }
template<typename CPU> template<typename CPU>
inline void MemoryOrRegisterReference::write16(CPU& cpu, const Instruction& insn, u16 value) ALWAYS_INLINE void MemoryOrRegisterReference::write16(CPU& cpu, const Instruction& insn, u16 value)
{ {
if (is_register()) { if (is_register()) {
cpu.gpr16(reg16()) = value; cpu.gpr16(reg16()) = value;
@ -600,7 +601,7 @@ inline void MemoryOrRegisterReference::write16(CPU& cpu, const Instruction& insn
} }
template<typename CPU> template<typename CPU>
inline void MemoryOrRegisterReference::write32(CPU& cpu, const Instruction& insn, u32 value) ALWAYS_INLINE void MemoryOrRegisterReference::write32(CPU& cpu, const Instruction& insn, u32 value)
{ {
if (is_register()) { if (is_register()) {
cpu.gpr32(reg32()) = value; cpu.gpr32(reg32()) = value;
@ -612,7 +613,7 @@ inline void MemoryOrRegisterReference::write32(CPU& cpu, const Instruction& insn
} }
template<typename CPU> template<typename CPU>
inline u8 MemoryOrRegisterReference::read8(CPU& cpu, const Instruction& insn) ALWAYS_INLINE u8 MemoryOrRegisterReference::read8(CPU& cpu, const Instruction& insn)
{ {
if (is_register()) if (is_register())
return cpu.gpr8(reg8()); return cpu.gpr8(reg8());
@ -622,7 +623,7 @@ inline u8 MemoryOrRegisterReference::read8(CPU& cpu, const Instruction& insn)
} }
template<typename CPU> template<typename CPU>
inline u16 MemoryOrRegisterReference::read16(CPU& cpu, const Instruction& insn) ALWAYS_INLINE u16 MemoryOrRegisterReference::read16(CPU& cpu, const Instruction& insn)
{ {
if (is_register()) if (is_register())
return cpu.gpr16(reg16()); return cpu.gpr16(reg16());
@ -632,7 +633,7 @@ inline u16 MemoryOrRegisterReference::read16(CPU& cpu, const Instruction& insn)
} }
template<typename CPU> template<typename CPU>
inline u32 MemoryOrRegisterReference::read32(CPU& cpu, const Instruction& insn) ALWAYS_INLINE u32 MemoryOrRegisterReference::read32(CPU& cpu, const Instruction& insn)
{ {
if (is_register()) if (is_register())
return cpu.gpr32(reg32()); return cpu.gpr32(reg32());