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https://github.com/RGBCube/serenity
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UserspaceEmulator: Mark some generic instructions ALWAYS_INLINE :^)
This commit is contained in:
Andreas Kling
parent
7ea36f5ed0
commit
f608b9d89a
1 changed files with 28 additions and 28 deletions
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@ -185,7 +185,7 @@ void SoftCPU::do_once_or_repeat(const X86::Instruction& insn, Callback callback)
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}
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template<typename T>
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static T op_inc(SoftCPU& cpu, T data)
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ALWAYS_INLINE static T op_inc(SoftCPU& cpu, T data)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -214,7 +214,7 @@ static T op_inc(SoftCPU& cpu, T data)
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}
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template<typename T>
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static T op_dec(SoftCPU& cpu, T data)
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ALWAYS_INLINE static T op_dec(SoftCPU& cpu, T data)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -243,7 +243,7 @@ static T op_dec(SoftCPU& cpu, T data)
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}
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template<typename T>
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static T op_xor(SoftCPU& cpu, const T& dest, const T& src)
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ALWAYS_INLINE static T op_xor(SoftCPU& cpu, const T& dest, const T& src)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -274,7 +274,7 @@ static T op_xor(SoftCPU& cpu, const T& dest, const T& src)
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}
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template<typename T>
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static T op_or(SoftCPU& cpu, const T& dest, const T& src)
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ALWAYS_INLINE static T op_or(SoftCPU& cpu, const T& dest, const T& src)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -305,7 +305,7 @@ static T op_or(SoftCPU& cpu, const T& dest, const T& src)
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}
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template<typename T>
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static T op_sub(SoftCPU& cpu, const T& dest, const T& src)
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ALWAYS_INLINE static T op_sub(SoftCPU& cpu, const T& dest, const T& src)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -336,7 +336,7 @@ static T op_sub(SoftCPU& cpu, const T& dest, const T& src)
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}
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template<typename T, bool cf>
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static T op_sbb_impl(SoftCPU& cpu, const T& dest, const T& src)
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ALWAYS_INLINE static T op_sbb_impl(SoftCPU& cpu, const T& dest, const T& src)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -372,7 +372,7 @@ static T op_sbb_impl(SoftCPU& cpu, const T& dest, const T& src)
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}
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template<typename T>
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static T op_sbb(SoftCPU& cpu, T& dest, const T& src)
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ALWAYS_INLINE static T op_sbb(SoftCPU& cpu, T& dest, const T& src)
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{
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if (cpu.cf())
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return op_sbb_impl<T, true>(cpu, dest, src);
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@ -380,7 +380,7 @@ static T op_sbb(SoftCPU& cpu, T& dest, const T& src)
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}
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template<typename T>
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static T op_add(SoftCPU& cpu, T& dest, const T& src)
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ALWAYS_INLINE static T op_add(SoftCPU& cpu, T& dest, const T& src)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -411,7 +411,7 @@ static T op_add(SoftCPU& cpu, T& dest, const T& src)
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}
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template<typename T, bool cf>
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static T op_adc_impl(SoftCPU& cpu, T& dest, const T& src)
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ALWAYS_INLINE static T op_adc_impl(SoftCPU& cpu, T& dest, const T& src)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -447,7 +447,7 @@ static T op_adc_impl(SoftCPU& cpu, T& dest, const T& src)
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}
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template<typename T>
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static T op_adc(SoftCPU& cpu, T& dest, const T& src)
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ALWAYS_INLINE static T op_adc(SoftCPU& cpu, T& dest, const T& src)
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{
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if (cpu.cf())
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return op_adc_impl<T, true>(cpu, dest, src);
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@ -455,7 +455,7 @@ static T op_adc(SoftCPU& cpu, T& dest, const T& src)
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}
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template<typename T>
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static T op_and(SoftCPU& cpu, const T& dest, const T& src)
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ALWAYS_INLINE static T op_and(SoftCPU& cpu, const T& dest, const T& src)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -486,7 +486,7 @@ static T op_and(SoftCPU& cpu, const T& dest, const T& src)
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}
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template<typename T>
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static T op_imul(SoftCPU& cpu, const T& dest, const T& src)
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ALWAYS_INLINE static T op_imul(SoftCPU& cpu, const T& dest, const T& src)
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{
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T result = 0;
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u32 new_flags = 0;
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@ -513,7 +513,7 @@ static T op_imul(SoftCPU& cpu, const T& dest, const T& src)
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}
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template<typename T>
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static T op_shr(SoftCPU& cpu, T data, u8 steps)
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ALWAYS_INLINE static T op_shr(SoftCPU& cpu, T data, u8 steps)
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{
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if (steps == 0)
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return data;
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@ -545,7 +545,7 @@ static T op_shr(SoftCPU& cpu, T data, u8 steps)
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}
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template<typename T>
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static T op_shl(SoftCPU& cpu, T data, u8 steps)
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ALWAYS_INLINE static T op_shl(SoftCPU& cpu, T data, u8 steps)
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{
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if (steps == 0)
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return data;
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@ -577,7 +577,7 @@ static T op_shl(SoftCPU& cpu, T data, u8 steps)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_AL_imm8(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_AL_imm8(Op op, const X86::Instruction& insn)
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{
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auto dest = al();
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auto src = insn.imm8();
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@ -587,7 +587,7 @@ void SoftCPU::generic_AL_imm8(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_AX_imm16(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_AX_imm16(Op op, const X86::Instruction& insn)
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{
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auto dest = ax();
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auto src = insn.imm16();
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@ -597,7 +597,7 @@ void SoftCPU::generic_AX_imm16(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_EAX_imm32(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_EAX_imm32(Op op, const X86::Instruction& insn)
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{
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auto dest = eax();
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auto src = insn.imm32();
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@ -607,7 +607,7 @@ void SoftCPU::generic_EAX_imm32(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_RM16_imm16(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_RM16_imm16(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read16(*this, insn);
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auto src = insn.imm16();
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@ -617,7 +617,7 @@ void SoftCPU::generic_RM16_imm16(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_RM16_imm8(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_RM16_imm8(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read16(*this, insn);
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auto src = sign_extended_to<u16>(insn.imm8());
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@ -627,7 +627,7 @@ void SoftCPU::generic_RM16_imm8(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_RM16_reg16(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_RM16_reg16(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read16(*this, insn);
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auto src = gpr16(insn.reg16());
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@ -637,7 +637,7 @@ void SoftCPU::generic_RM16_reg16(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_RM32_imm32(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_RM32_imm32(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read32(*this, insn);
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auto src = insn.imm32();
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@ -647,7 +647,7 @@ void SoftCPU::generic_RM32_imm32(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_RM32_imm8(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_RM32_imm8(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read32(*this, insn);
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auto src = sign_extended_to<u32>(insn.imm8());
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@ -657,7 +657,7 @@ void SoftCPU::generic_RM32_imm8(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_RM32_reg32(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_RM32_reg32(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read32(*this, insn);
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auto src = gpr32(insn.reg32());
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@ -667,7 +667,7 @@ void SoftCPU::generic_RM32_reg32(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_RM8_imm8(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_RM8_imm8(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read8(*this, insn);
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auto src = insn.imm8();
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@ -677,7 +677,7 @@ void SoftCPU::generic_RM8_imm8(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_RM8_reg8(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_RM8_reg8(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read8(*this, insn);
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auto src = gpr8(insn.reg8());
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@ -687,7 +687,7 @@ void SoftCPU::generic_RM8_reg8(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_reg16_RM16(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_reg16_RM16(Op op, const X86::Instruction& insn)
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{
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auto dest = gpr16(insn.reg16());
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auto src = insn.modrm().read16(*this, insn);
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@ -697,7 +697,7 @@ void SoftCPU::generic_reg16_RM16(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_reg32_RM32(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_reg32_RM32(Op op, const X86::Instruction& insn)
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{
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auto dest = gpr32(insn.reg32());
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auto src = insn.modrm().read32(*this, insn);
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@ -707,7 +707,7 @@ void SoftCPU::generic_reg32_RM32(Op op, const X86::Instruction& insn)
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}
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template<bool update_dest, typename Op>
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void SoftCPU::generic_reg8_RM8(Op op, const X86::Instruction& insn)
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ALWAYS_INLINE void SoftCPU::generic_reg8_RM8(Op op, const X86::Instruction& insn)
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{
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auto dest = gpr8(insn.reg8());
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auto src = insn.modrm().read8(*this, insn);
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