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LibX86: Support disassembling a few FPU opcodes better
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commit
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5 changed files with 126 additions and 6 deletions
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@ -82,6 +82,8 @@ enum InstructionFormat {
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OP_RM8,
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OP_RM16,
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OP_RM32,
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OP_FPU_RM32,
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OP_FPU_RM64,
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OP_RM8_reg8,
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OP_RM32_reg32,
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OP_reg32_RM32,
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@ -256,6 +258,17 @@ enum RegisterIndex32 {
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RegisterEDI
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};
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enum FpuRegisterIndex {
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ST0 = 0,
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ST1,
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ST2,
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ST3,
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ST4,
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ST5,
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ST6,
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ST7
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};
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enum MMXRegisterIndex {
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RegisterMM0 = 0,
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RegisterMM1,
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@ -339,6 +352,8 @@ public:
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String to_string_o8(const Instruction&) const;
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String to_string_o16(const Instruction&) const;
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String to_string_o32(const Instruction&) const;
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String to_string_fpu32(const Instruction&) const;
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String to_string_fpu64(const Instruction&) const;
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String to_string_mm(const Instruction&) const;
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bool is_register() const { return m_register_index != 0xffffffff; }
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@ -347,6 +362,7 @@ public:
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RegisterIndex32 reg32() const { return static_cast<RegisterIndex32>(register_index()); }
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RegisterIndex16 reg16() const { return static_cast<RegisterIndex16>(register_index()); }
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RegisterIndex8 reg8() const { return static_cast<RegisterIndex8>(register_index()); }
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FpuRegisterIndex reg_fpu() const { return static_cast<FpuRegisterIndex>(register_index()); }
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template<typename CPU, typename T>
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void write8(CPU&, const Instruction&, T);
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