From fea23d0ec100ab7773617ef98d9c9378a5f50e36 Mon Sep 17 00:00:00 2001
From: Jean-Baptiste Boric <jblbeurope@gmail.com>
Date: Mon, 14 Jun 2021 23:59:38 +0200
Subject: [PATCH] Kernel: Detect support for CPUID FXSR

The fxsave and fxrstor instructions are available only if the FXSR
feature is present.
---
 Kernel/Arch/i386/CPU.cpp | 4 ++++
 Kernel/Arch/x86/CPU.h    | 1 +
 2 files changed, 5 insertions(+)

diff --git a/Kernel/Arch/i386/CPU.cpp b/Kernel/Arch/i386/CPU.cpp
index a83beac00a..24bf137685 100644
--- a/Kernel/Arch/i386/CPU.cpp
+++ b/Kernel/Arch/i386/CPU.cpp
@@ -971,6 +971,8 @@ UNMAP_AFTER_INIT void Processor::cpu_detect()
         set_feature(CPUFeature::PGE);
     if (processor_info.edx() & (1 << 23))
         set_feature(CPUFeature::MMX);
+    if (processor_info.edx() & (1 << 24))
+        set_feature(CPUFeature::FXSR);
     if (processor_info.edx() & (1 << 25))
         set_feature(CPUFeature::SSE);
     if (processor_info.edx() & (1 << 26))
@@ -1137,6 +1139,8 @@ String Processor::features_string() const
             return "syscall";
         case CPUFeature::MMX:
             return "mmx";
+        case CPUFeature::FXSR:
+            return "fxsr";
         case CPUFeature::SSE2:
             return "sse2";
         case CPUFeature::SSE3:
diff --git a/Kernel/Arch/x86/CPU.h b/Kernel/Arch/x86/CPU.h
index d17e1ffb23..c1baf2478c 100644
--- a/Kernel/Arch/x86/CPU.h
+++ b/Kernel/Arch/x86/CPU.h
@@ -548,6 +548,7 @@ enum class CPUFeature : u32 {
     SSE4_2 = (1 << 20),
     XSAVE = (1 << 21),
     AVX = (1 << 22),
+    FXSR = (1 << 23),
 };
 
 class Thread;