serenity

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Author SHA1 Message Date

Author	SHA1	Message	Date
Sönke Holz	1429c83942	Kernel/riscv64: Implement {load,store}_fpu_state This commit adds two functions which save/restore the entire FPU state. On RISC-V, you only need to save the floating pointer registers themselves and the fcsr CSR, which contains the entire state of the F/D extensions.	2024-02-24 16:42:58 -07:00
Sönke Holz	ac79ab0b45	Kernel/riscv64: Specify correct alignment for `FPUState` struct The signal handling code (and possibly other code as well) expects this struct to have an alignment of 16 bytes, as it pushes this struct on the stack.	2023-12-16 18:21:03 +01:00
Sönke Holz	24e64cac7e	Kernel/riscv64: Add register state related headers	2023-10-28 10:36:06 -06:00

Sönke Holz

1429c83942

Kernel/riscv64: Implement {load,store}_fpu_state

This commit adds two functions which save/restore the entire FPU state.
On RISC-V, you only need to save the floating pointer registers
themselves and the fcsr CSR, which contains the entire state of the F/D
extensions.

2024-02-24 16:42:58 -07:00

Sönke Holz

ac79ab0b45

Kernel/riscv64: Specify correct alignment for FPUState struct

The signal handling code (and possibly other code as well) expects this
struct to have an alignment of 16 bytes, as it pushes this struct on the
stack.

2023-12-16 18:21:03 +01:00

Sönke Holz

24e64cac7e

Kernel/riscv64: Add register state related headers

2023-10-28 10:36:06 -06:00

3 commits