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10 commits

Author SHA1 Message Date
Sönke Holz
1fc0c84017 Kernel/riscv64: Implement Processor::assume_context
This code is based on the aarch64 implementation.
2024-02-24 16:42:58 -07:00
Sönke Holz
726865592c Kernel/riscv64: Implement Processor::switch_context
This code is based on the aarch64 implementation.
2024-02-24 16:42:58 -07:00
Sönke Holz
494e026ca7 Kernel/riscv64: Implement Processor::init_context
This code is based on the aarch64 implementation.
2024-02-24 16:42:58 -07:00
Sönke Holz
efdc433ebc Kernel/riscv64: Implement thread_context_first_enter
thread_context_first_enter reuses the context restoring code in the
trap handler, just like other arches already do.

The `ld x2, 1*8(sp)` is unnecessary in the trap handler, as the stack
pointer should be equal to the stack pointer slot in the RegisterState
if the trap is from supervisor mode (and we currently don't support
user traps).
This load will however make us unable to reuse that code for
thread_context_first_enter.
2024-02-24 16:42:58 -07:00
Sönke Holz
7fbcceb657 Kernel/riscv64: Implement enter_thread_context
This code is based on the aarch64 implementation.
2024-02-24 16:42:58 -07:00
Sönke Holz
2f33e7a964 Kernel/riscv64: Stub out Processor::set_thread_specific_data 2024-02-24 16:42:58 -07:00
Sönke Holz
7fff6eef09 Kernel/riscv64: Implement Processor::initialize_context_switching
This code is based on the aarch64 implementation.
2024-02-24 16:42:58 -07:00
Sönke Holz
1429c83942 Kernel/riscv64: Implement {load,store}_fpu_state
This commit adds two functions which save/restore the entire FPU state.
On RISC-V, you only need to save the floating pointer registers
themselves and the fcsr CSR, which contains the entire state of the F/D
extensions.
2024-02-24 16:42:58 -07:00
Sönke Holz
0111fe0d24 Kernel/riscv64: Implement Processor::exit_trap
This function is copy-pasted from aarch64's Processor.cpp
2024-01-23 13:13:18 -07:00
Sönke Holz
194bf5a677 Kernel/riscv64: Add RISC-V Processor class 2023-10-28 10:36:06 -06:00