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2 commits

Author SHA1 Message Date
Liav A
cf0a12c68f Kernel: Add various methods to handle interrupts in the PCI subsystem
For now, we only are able to enable or disable pin based interrupts.
Later, when implemented, we could utilize MSI & MSI-X interrupts.
2020-12-21 00:19:21 +01:00
Liav A
9d10eb473d Kernel: Add the DeviceController class in the PCI subsystem
Such device is not an IRQHandler by itself, but actually a controller of
many IRQ or MSI devices. The purpose of this class is to manage multiple
sources of interrupts.

For example, a generic ISA IDE controller controls 2 IRQ sources - 14
and 15. So, when we initialize the IDE controller, it will initialize
two IDE channels (also known as PATAChannels) to utilize IRQ 14 and 15,
respectively. NVMe with MSI-X support can theoretically handle up to
2048 interrupts.
2020-12-21 00:19:21 +01:00