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8 commits

Author SHA1 Message Date
Pankaj Raghav
4a8a3df975 Kernel: Fix index calculation in NVMeQueue submit_sync_sqe function
There was a bug while calculating the next index in submit_sync_sqe
function. Use the NVMeQueue's class variable m_qdepth instead of the
hardcoded IO_QUEUE_SIZE.
2022-01-25 20:06:19 +02:00
Liav A
fc2c2c8a6d Kernel/Storage: Remove NVMeQueue DMA buffer create method
Instead, try to allocate the DMA buffer before trying to construct the
NVMeQueue. This allows us to fail early if we can't allocate the DMA
buffer before allocating and creating the heavier NVMeQueue object.
2022-01-23 20:56:28 +00:00
Liav A
0778043d73 Kernel: Use generic string when allocating DMA buffer to NVMeQueue
We don't necessarily create a DMA buffer just for "Admin CQ queue", so
don't hardcode it when allocating such buffer.
2022-01-23 20:56:28 +00:00
Liav A
0536079ad8 Kernel/Storage: Use StringView when allocating DMA buffer in NVMeQueue 2022-01-23 20:56:28 +00:00
Pankaj Raghav
567b3a4810 Kernel: Add individual struct definitions for NVMeSubmission
Only a generic struct definition was present for NVMeSubmission. To
improve type safety and clarity, added an union of NVMeSubmission
structs that are applicable to the command being submitted.
2022-01-18 11:37:04 +02:00
Pankaj Raghav
31c4c9724b Kernel: Add UNMAP_AFTER_INIT to NVMe member functions
NVMeController, NVMeQueue and NVMeNameSpace had functions which are not
used after init. So add them to UNMAP_AFTER_INIT section.
2022-01-18 11:37:04 +02:00
Tom
d1e7b69004 Kernel: Fix NVMe register access
We need to use the volatile keyword when mapping the device registers,
or the compiler may optimize access, which lead to this QEMU error:

pci_nvme_ub_mmiord_toosmall in nvme_mmio_read: MMIO read smaller than
32-bits, offset=0x0
2022-01-01 21:05:44 +00:00
Pankaj Raghav
e99fafb683 Kernel/NVMe: Add initial NVMe driver support
Add a basic NVMe driver support to serenity
based on NVMe spec 1.4.

The driver can support multiple NVMe drives (subsystems).
But in a NVMe drive, the driver can support one controller
with multiple namespaces.

Each core will get a separate NVMe Queue.
As the system lacks MSI support, PIN based interrupts are
used for IO.

Tested the NVMe support by replacing IDE driver
with the NVMe driver :^)
2022-01-01 14:55:58 +01:00