mirror of
https://github.com/RGBCube/serenity
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1005 lines
26 KiB
C++
1005 lines
26 KiB
C++
/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#pragma once
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#include <AK/Optional.h>
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#include <AK/StdLibExtras.h>
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#include <AK/String.h>
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#include <AK/Types.h>
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#include <stdio.h>
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namespace X86 {
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class Instruction;
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class Interpreter;
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typedef void (Interpreter::*InstructionHandler)(const Instruction&);
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class SymbolProvider {
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public:
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virtual String symbolicate(FlatPtr, u32* offset = nullptr) const = 0;
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};
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template<typename T>
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struct TypeTrivia {
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static const size_t bits = sizeof(T) * 8;
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static const T sign_bit = 1 << (bits - 1);
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static const T mask = typename MakeUnsigned<T>::Type(-1);
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};
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template<typename T, typename U>
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constexpr T sign_extended_to(U value)
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{
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if (!(value & TypeTrivia<U>::sign_bit))
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return value;
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return (TypeTrivia<T>::mask & ~TypeTrivia<U>::mask) | value;
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}
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enum IsLockPrefixAllowed {
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LockPrefixNotAllowed = 0,
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LockPrefixAllowed
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};
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enum InstructionFormat {
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InvalidFormat,
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MultibyteWithSlash,
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InstructionPrefix,
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__BeginFormatsWithRMByte,
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OP_RM16_reg16,
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OP_reg8_RM8,
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OP_reg16_RM16,
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OP_RM16_seg,
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OP_RM32_seg,
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OP_RM8_imm8,
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OP_RM16_imm16,
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OP_RM16_imm8,
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OP_RM32_imm8,
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OP_RM8,
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OP_RM16,
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OP_RM32,
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OP_FPU,
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OP_FPU_reg,
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OP_FPU_mem,
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OP_FPU_AX16,
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OP_FPU_RM16,
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OP_FPU_RM32,
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OP_FPU_RM64,
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OP_FPU_M80,
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OP_RM8_reg8,
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OP_RM32_reg32,
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OP_reg32_RM32,
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OP_RM32_imm32,
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OP_reg16_RM16_imm8,
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OP_reg32_RM32_imm8,
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OP_reg16_RM16_imm16,
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OP_reg32_RM32_imm32,
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OP_reg16_mem16,
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OP_reg32_mem32,
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OP_seg_RM16,
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OP_seg_RM32,
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OP_RM8_1,
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OP_RM16_1,
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OP_RM32_1,
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OP_FAR_mem16,
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OP_FAR_mem32,
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OP_RM8_CL,
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OP_RM16_CL,
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OP_RM32_CL,
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OP_reg32_CR,
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OP_CR_reg32,
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OP_reg32_DR,
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OP_DR_reg32,
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OP_reg16_RM8,
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OP_reg32_RM8,
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OP_reg32_RM16,
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OP_RM16_reg16_imm8,
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OP_RM32_reg32_imm8,
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OP_RM16_reg16_CL,
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OP_RM32_reg32_CL,
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OP_mm1_mm2m64,
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OP_mm1m64_mm2,
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__EndFormatsWithRMByte,
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OP_reg32_imm32,
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OP_AL_imm8,
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OP_AX_imm16,
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OP_EAX_imm32,
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OP_CS,
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OP_DS,
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OP_ES,
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OP_SS,
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OP_FS,
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OP_GS,
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OP,
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OP_reg16,
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OP_imm16,
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OP_relimm16,
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OP_relimm32,
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OP_imm8,
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OP_imm16_imm16,
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OP_imm16_imm32,
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OP_AX_reg16,
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OP_EAX_reg32,
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OP_AL_moff8,
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OP_AX_moff16,
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OP_EAX_moff32,
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OP_moff8_AL,
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OP_moff16_AX,
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OP_moff32_EAX,
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OP_reg8_imm8,
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OP_reg16_imm16,
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OP_3,
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OP_AX_imm8,
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OP_EAX_imm8,
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OP_short_imm8,
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OP_AL_DX,
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OP_AX_DX,
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OP_EAX_DX,
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OP_DX_AL,
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OP_DX_AX,
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OP_DX_EAX,
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OP_imm8_AL,
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OP_imm8_AX,
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OP_imm8_EAX,
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OP_reg8_CL,
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OP_reg32,
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OP_imm32,
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OP_imm16_imm8,
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OP_NEAR_imm,
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};
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static const unsigned CurrentAddressSize = 0xB33FBABE;
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struct InstructionDescriptor {
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InstructionHandler handler { nullptr };
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bool opcode_has_register_index { false };
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const char* mnemonic { nullptr };
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InstructionFormat format { InvalidFormat };
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bool has_rm { false };
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unsigned imm1_bytes { 0 };
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unsigned imm2_bytes { 0 };
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// Addressed by the 3 REG bits in the MOD-REG-R/M byte.
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// Some slash instructions have further subgroups when MOD is 11,
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// in that case the InstructionDescriptors in slashes have themselves
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// a non-null slashes member that's indexed by the three R/M bits.
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InstructionDescriptor* slashes { nullptr };
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unsigned imm1_bytes_for_address_size(bool a32)
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{
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if (imm1_bytes == CurrentAddressSize)
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return a32 ? 4 : 2;
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return imm1_bytes;
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}
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unsigned imm2_bytes_for_address_size(bool a32)
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{
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if (imm2_bytes == CurrentAddressSize)
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return a32 ? 4 : 2;
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return imm2_bytes;
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}
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IsLockPrefixAllowed lock_prefix_allowed { LockPrefixNotAllowed };
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};
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extern InstructionDescriptor s_table16[256];
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extern InstructionDescriptor s_table32[256];
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extern InstructionDescriptor s_0f_table16[256];
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extern InstructionDescriptor s_0f_table32[256];
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struct Prefix {
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enum Op {
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OperandSizeOverride = 0x66,
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AddressSizeOverride = 0x67,
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REP = 0xf3,
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REPZ = 0xf3,
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REPNZ = 0xf2,
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LOCK = 0xf0,
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};
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};
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enum class SegmentRegister {
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ES = 0,
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CS,
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SS,
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DS,
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FS,
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GS,
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SegR6,
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SegR7,
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};
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enum RegisterIndex8 {
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RegisterAL = 0,
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RegisterCL,
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RegisterDL,
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RegisterBL,
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RegisterAH,
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RegisterCH,
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RegisterDH,
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RegisterBH
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};
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enum RegisterIndex16 {
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RegisterAX = 0,
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RegisterCX,
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RegisterDX,
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RegisterBX,
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RegisterSP,
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RegisterBP,
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RegisterSI,
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RegisterDI
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};
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enum RegisterIndex32 {
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RegisterEAX = 0,
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RegisterECX,
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RegisterEDX,
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RegisterEBX,
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RegisterESP,
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RegisterEBP,
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RegisterESI,
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RegisterEDI
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};
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enum FpuRegisterIndex {
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ST0 = 0,
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ST1,
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ST2,
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ST3,
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ST4,
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ST5,
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ST6,
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ST7
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};
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enum MMXRegisterIndex {
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RegisterMM0 = 0,
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RegisterMM1,
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RegisterMM2,
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RegisterMM3,
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RegisterMM4,
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RegisterMM5,
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RegisterMM6,
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RegisterMM7
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};
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class LogicalAddress {
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public:
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LogicalAddress() { }
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LogicalAddress(u16 selector, u32 offset)
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: m_selector(selector)
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, m_offset(offset)
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{
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}
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u16 selector() const { return m_selector; }
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u32 offset() const { return m_offset; }
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void set_selector(u16 selector) { m_selector = selector; }
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void set_offset(u32 offset) { m_offset = offset; }
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private:
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u16 m_selector { 0 };
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u32 m_offset { 0 };
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};
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class InstructionStream {
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public:
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virtual bool can_read() = 0;
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virtual u8 read8() = 0;
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virtual u16 read16() = 0;
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virtual u32 read32() = 0;
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virtual u64 read64() = 0;
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};
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class SimpleInstructionStream final : public InstructionStream {
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public:
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SimpleInstructionStream(const u8* data, size_t size)
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: m_data(data)
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, m_size(size)
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{
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}
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virtual bool can_read() override { return m_offset < m_size; }
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virtual u8 read8() override
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{
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if (!can_read())
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return 0;
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return m_data[m_offset++];
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}
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virtual u16 read16() override
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{
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u8 lsb = read8();
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u8 msb = read8();
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return ((u16)msb << 8) | (u16)lsb;
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}
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virtual u32 read32() override
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{
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u16 lsw = read16();
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u16 msw = read16();
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return ((u32)msw << 16) | (u32)lsw;
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}
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virtual u64 read64() override
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{
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u32 lsw = read32();
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u32 msw = read32();
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return ((u64)msw << 32) | (u64)lsw;
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}
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size_t offset() const { return m_offset; }
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private:
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const u8* m_data { nullptr };
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size_t m_offset { 0 };
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size_t m_size { 0 };
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};
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class MemoryOrRegisterReference {
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friend class Instruction;
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public:
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String to_string_o8(const Instruction&) const;
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String to_string_o16(const Instruction&) const;
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String to_string_o32(const Instruction&) const;
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String to_string_fpu_reg() const;
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String to_string_fpu_mem(const Instruction&) const;
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String to_string_fpu_ax16() const;
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String to_string_fpu16(const Instruction&) const;
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String to_string_fpu32(const Instruction&) const;
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String to_string_fpu64(const Instruction&) const;
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String to_string_fpu80(const Instruction&) const;
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String to_string_mm(const Instruction&) const;
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bool is_register() const { return m_register_index != 0x7f; }
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unsigned register_index() const { return m_register_index; }
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RegisterIndex32 reg32() const { return static_cast<RegisterIndex32>(register_index()); }
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RegisterIndex16 reg16() const { return static_cast<RegisterIndex16>(register_index()); }
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RegisterIndex8 reg8() const { return static_cast<RegisterIndex8>(register_index()); }
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FpuRegisterIndex reg_fpu() const { return static_cast<FpuRegisterIndex>(register_index()); }
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template<typename CPU, typename T>
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void write8(CPU&, const Instruction&, T);
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template<typename CPU, typename T>
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void write16(CPU&, const Instruction&, T);
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template<typename CPU, typename T>
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void write32(CPU&, const Instruction&, T);
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template<typename CPU, typename T>
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void write64(CPU&, const Instruction&, T);
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template<typename CPU>
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typename CPU::ValueWithShadowType8 read8(CPU&, const Instruction&);
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template<typename CPU>
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typename CPU::ValueWithShadowType16 read16(CPU&, const Instruction&);
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template<typename CPU>
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typename CPU::ValueWithShadowType32 read32(CPU&, const Instruction&);
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template<typename CPU>
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typename CPU::ValueWithShadowType64 read64(CPU&, const Instruction&);
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template<typename CPU>
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LogicalAddress resolve(const CPU&, const Instruction&);
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private:
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MemoryOrRegisterReference() { }
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String to_string(const Instruction&) const;
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String to_string_a16() const;
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String to_string_a32() const;
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template<typename InstructionStreamType>
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void decode(InstructionStreamType&, bool a32);
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template<typename InstructionStreamType>
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void decode16(InstructionStreamType&);
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template<typename InstructionStreamType>
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void decode32(InstructionStreamType&);
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template<typename CPU>
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LogicalAddress resolve16(const CPU&, Optional<SegmentRegister>);
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template<typename CPU>
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LogicalAddress resolve32(const CPU&, Optional<SegmentRegister>);
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template<typename CPU>
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u32 evaluate_sib(const CPU&, SegmentRegister& default_segment) const;
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union {
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u32 m_displacement32 { 0 };
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u16 m_displacement16;
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};
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u8 m_rm { 0 };
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u8 m_sib { 0 };
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u8 m_displacement_bytes { 0 };
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u8 m_register_index : 7 { 0x7f };
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bool m_has_sib : 1 { false };
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};
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class Instruction {
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public:
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template<typename InstructionStreamType>
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static Instruction from_stream(InstructionStreamType&, bool o32, bool a32);
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~Instruction() { }
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ALWAYS_INLINE MemoryOrRegisterReference& modrm() const { return m_modrm; }
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ALWAYS_INLINE InstructionHandler handler() const { return m_descriptor->handler; }
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bool has_segment_prefix() const { return m_segment_prefix != 0xff; }
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ALWAYS_INLINE Optional<SegmentRegister> segment_prefix() const
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{
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if (has_segment_prefix())
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return static_cast<SegmentRegister>(m_segment_prefix);
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return {};
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}
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bool has_address_size_override_prefix() const { return m_has_address_size_override_prefix; }
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bool has_operand_size_override_prefix() const { return m_has_operand_size_override_prefix; }
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bool has_lock_prefix() const { return m_has_lock_prefix; }
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bool has_rep_prefix() const { return m_rep_prefix; }
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u8 rep_prefix() const { return m_rep_prefix; }
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bool is_valid() const { return m_descriptor; }
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unsigned length() const;
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String mnemonic() const;
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u8 op() const { return m_op; }
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u8 rm() const { return m_modrm.m_rm; }
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u8 slash() const { return (rm() >> 3) & 7; }
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u8 imm8() const { return m_imm1; }
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u16 imm16() const { return m_imm1; }
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u32 imm32() const { return m_imm1; }
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u8 imm8_1() const { return imm8(); }
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u8 imm8_2() const { return m_imm2; }
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u16 imm16_1() const { return imm16(); }
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u16 imm16_2() const { return m_imm2; }
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u32 imm32_1() const { return imm32(); }
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u32 imm32_2() const { return m_imm2; }
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u32 imm_address() const { return m_a32 ? imm32() : imm16(); }
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LogicalAddress imm_address16_16() const { return LogicalAddress(imm16_1(), imm16_2()); }
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LogicalAddress imm_address16_32() const { return LogicalAddress(imm16_1(), imm32_2()); }
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bool has_sub_op() const
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{
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return m_op == 0x0f;
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}
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unsigned register_index() const { return m_register_index; }
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RegisterIndex32 reg32() const { return static_cast<RegisterIndex32>(register_index()); }
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RegisterIndex16 reg16() const { return static_cast<RegisterIndex16>(register_index()); }
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RegisterIndex8 reg8() const { return static_cast<RegisterIndex8>(register_index()); }
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SegmentRegister segment_register() const { return static_cast<SegmentRegister>(register_index()); }
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u8 cc() const { return has_sub_op() ? m_sub_op & 0xf : m_op & 0xf; }
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bool a32() const { return m_a32; }
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String to_string(u32 origin, const SymbolProvider* = nullptr, bool x32 = true) const;
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private:
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template<typename InstructionStreamType>
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Instruction(InstructionStreamType&, bool o32, bool a32);
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void to_string_internal(StringBuilder&, u32 origin, const SymbolProvider*, bool x32) const;
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const char* reg8_name() const;
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const char* reg16_name() const;
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const char* reg32_name() const;
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InstructionDescriptor* m_descriptor { nullptr };
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mutable MemoryOrRegisterReference m_modrm;
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u32 m_imm1 { 0 };
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u32 m_imm2 { 0 };
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u8 m_segment_prefix { 0xff };
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u8 m_register_index { 0xff };
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u8 m_op { 0 };
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u8 m_sub_op { 0 };
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u8 m_extra_bytes { 0 };
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u8 m_rep_prefix { 0 };
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bool m_a32 : 1 { false };
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bool m_o32 : 1 { false };
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bool m_has_lock_prefix : 1 { false };
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bool m_has_operand_size_override_prefix : 1 { false };
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bool m_has_address_size_override_prefix : 1 { false };
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};
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template<typename CPU>
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ALWAYS_INLINE LogicalAddress MemoryOrRegisterReference::resolve16(const CPU& cpu, Optional<SegmentRegister> segment_prefix)
|
|
{
|
|
auto default_segment = SegmentRegister::DS;
|
|
u16 offset = 0;
|
|
|
|
switch (m_rm & 7) {
|
|
case 0:
|
|
offset = cpu.bx().value() + cpu.si().value() + m_displacement16;
|
|
break;
|
|
case 1:
|
|
offset = cpu.bx().value() + cpu.di().value() + m_displacement16;
|
|
break;
|
|
case 2:
|
|
default_segment = SegmentRegister::SS;
|
|
offset = cpu.bp().value() + cpu.si().value() + m_displacement16;
|
|
break;
|
|
case 3:
|
|
default_segment = SegmentRegister::SS;
|
|
offset = cpu.bp().value() + cpu.di().value() + m_displacement16;
|
|
break;
|
|
case 4:
|
|
offset = cpu.si().value() + m_displacement16;
|
|
break;
|
|
case 5:
|
|
offset = cpu.di().value() + m_displacement16;
|
|
break;
|
|
case 6:
|
|
if ((m_rm & 0xc0) == 0)
|
|
offset = m_displacement16;
|
|
else {
|
|
default_segment = SegmentRegister::SS;
|
|
offset = cpu.bp().value() + m_displacement16;
|
|
}
|
|
break;
|
|
default:
|
|
offset = cpu.bx().value() + m_displacement16;
|
|
break;
|
|
}
|
|
|
|
u16 segment = cpu.segment(segment_prefix.value_or(default_segment));
|
|
return { segment, offset };
|
|
}
|
|
|
|
template<typename CPU>
|
|
ALWAYS_INLINE LogicalAddress MemoryOrRegisterReference::resolve32(const CPU& cpu, Optional<SegmentRegister> segment_prefix)
|
|
{
|
|
auto default_segment = SegmentRegister::DS;
|
|
u32 offset = 0;
|
|
|
|
switch (m_rm & 0x07) {
|
|
case 0 ... 3:
|
|
case 6 ... 7:
|
|
offset = cpu.const_gpr32((RegisterIndex32)(m_rm & 0x07)).value() + m_displacement32;
|
|
break;
|
|
case 4:
|
|
offset = evaluate_sib(cpu, default_segment);
|
|
break;
|
|
default: // 5
|
|
if ((m_rm & 0xc0) == 0x00) {
|
|
offset = m_displacement32;
|
|
break;
|
|
} else {
|
|
default_segment = SegmentRegister::SS;
|
|
offset = cpu.ebp().value() + m_displacement32;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
u16 segment = cpu.segment(segment_prefix.value_or(default_segment));
|
|
return { segment, offset };
|
|
}
|
|
|
|
template<typename CPU>
|
|
ALWAYS_INLINE u32 MemoryOrRegisterReference::evaluate_sib(const CPU& cpu, SegmentRegister& default_segment) const
|
|
{
|
|
u32 scale_shift = m_sib >> 6;
|
|
u32 index = 0;
|
|
switch ((m_sib >> 3) & 0x07) {
|
|
case 0 ... 3:
|
|
case 5 ... 7:
|
|
index = cpu.const_gpr32((RegisterIndex32)((m_sib >> 3) & 0x07)).value();
|
|
break;
|
|
case 4:
|
|
index = 0;
|
|
break;
|
|
}
|
|
|
|
u32 base = m_displacement32;
|
|
switch (m_sib & 0x07) {
|
|
case 0 ... 3:
|
|
case 6 ... 7:
|
|
base += cpu.const_gpr32((RegisterIndex32)(m_sib & 0x07)).value();
|
|
break;
|
|
case 4:
|
|
default_segment = SegmentRegister::SS;
|
|
base += cpu.esp().value();
|
|
break;
|
|
default: // 5
|
|
switch ((m_rm >> 6) & 3) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
case 2:
|
|
default_segment = SegmentRegister::SS;
|
|
base += cpu.ebp().value();
|
|
break;
|
|
default:
|
|
ASSERT_NOT_REACHED();
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
return (index << scale_shift) + base;
|
|
}
|
|
|
|
template<typename CPU, typename T>
|
|
ALWAYS_INLINE void MemoryOrRegisterReference::write8(CPU& cpu, const Instruction& insn, T value)
|
|
{
|
|
if (is_register()) {
|
|
cpu.gpr8(reg8()) = value;
|
|
return;
|
|
}
|
|
|
|
auto address = resolve(cpu, insn);
|
|
cpu.write_memory8(address, value);
|
|
}
|
|
|
|
template<typename CPU, typename T>
|
|
ALWAYS_INLINE void MemoryOrRegisterReference::write16(CPU& cpu, const Instruction& insn, T value)
|
|
{
|
|
if (is_register()) {
|
|
cpu.gpr16(reg16()) = value;
|
|
return;
|
|
}
|
|
|
|
auto address = resolve(cpu, insn);
|
|
cpu.write_memory16(address, value);
|
|
}
|
|
|
|
template<typename CPU, typename T>
|
|
ALWAYS_INLINE void MemoryOrRegisterReference::write32(CPU& cpu, const Instruction& insn, T value)
|
|
{
|
|
if (is_register()) {
|
|
cpu.gpr32(reg32()) = value;
|
|
return;
|
|
}
|
|
|
|
auto address = resolve(cpu, insn);
|
|
cpu.write_memory32(address, value);
|
|
}
|
|
|
|
template<typename CPU, typename T>
|
|
ALWAYS_INLINE void MemoryOrRegisterReference::write64(CPU& cpu, const Instruction& insn, T value)
|
|
{
|
|
ASSERT(!is_register());
|
|
auto address = resolve(cpu, insn);
|
|
cpu.write_memory64(address, value);
|
|
}
|
|
|
|
template<typename CPU>
|
|
ALWAYS_INLINE typename CPU::ValueWithShadowType8 MemoryOrRegisterReference::read8(CPU& cpu, const Instruction& insn)
|
|
{
|
|
if (is_register())
|
|
return cpu.const_gpr8(reg8());
|
|
|
|
auto address = resolve(cpu, insn);
|
|
return cpu.read_memory8(address);
|
|
}
|
|
|
|
template<typename CPU>
|
|
ALWAYS_INLINE typename CPU::ValueWithShadowType16 MemoryOrRegisterReference::read16(CPU& cpu, const Instruction& insn)
|
|
{
|
|
if (is_register())
|
|
return cpu.const_gpr16(reg16());
|
|
|
|
auto address = resolve(cpu, insn);
|
|
return cpu.read_memory16(address);
|
|
}
|
|
|
|
template<typename CPU>
|
|
ALWAYS_INLINE typename CPU::ValueWithShadowType32 MemoryOrRegisterReference::read32(CPU& cpu, const Instruction& insn)
|
|
{
|
|
if (is_register())
|
|
return cpu.const_gpr32(reg32());
|
|
|
|
auto address = resolve(cpu, insn);
|
|
return cpu.read_memory32(address);
|
|
}
|
|
|
|
template<typename CPU>
|
|
ALWAYS_INLINE typename CPU::ValueWithShadowType64 MemoryOrRegisterReference::read64(CPU& cpu, const Instruction& insn)
|
|
{
|
|
ASSERT(!is_register());
|
|
auto address = resolve(cpu, insn);
|
|
return cpu.read_memory64(address);
|
|
}
|
|
|
|
template<typename InstructionStreamType>
|
|
ALWAYS_INLINE Instruction Instruction::from_stream(InstructionStreamType& stream, bool o32, bool a32)
|
|
{
|
|
return Instruction(stream, o32, a32);
|
|
}
|
|
|
|
ALWAYS_INLINE unsigned Instruction::length() const
|
|
{
|
|
unsigned len = 1;
|
|
if (has_sub_op())
|
|
++len;
|
|
if (m_descriptor->has_rm) {
|
|
++len;
|
|
if (m_modrm.m_has_sib)
|
|
++len;
|
|
len += m_modrm.m_displacement_bytes;
|
|
}
|
|
len += m_extra_bytes;
|
|
return len;
|
|
}
|
|
|
|
ALWAYS_INLINE Optional<SegmentRegister> to_segment_prefix(u8 op)
|
|
{
|
|
switch (op) {
|
|
case 0x26:
|
|
return SegmentRegister::ES;
|
|
case 0x2e:
|
|
return SegmentRegister::CS;
|
|
case 0x36:
|
|
return SegmentRegister::SS;
|
|
case 0x3e:
|
|
return SegmentRegister::DS;
|
|
case 0x64:
|
|
return SegmentRegister::FS;
|
|
case 0x65:
|
|
return SegmentRegister::GS;
|
|
default:
|
|
return {};
|
|
}
|
|
}
|
|
|
|
template<typename InstructionStreamType>
|
|
ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32, bool a32)
|
|
: m_a32(a32)
|
|
, m_o32(o32)
|
|
{
|
|
u8 prefix_bytes = 0;
|
|
for (;; ++prefix_bytes) {
|
|
u8 opbyte = stream.read8();
|
|
if (opbyte == Prefix::OperandSizeOverride) {
|
|
m_o32 = !o32;
|
|
m_has_operand_size_override_prefix = true;
|
|
continue;
|
|
}
|
|
if (opbyte == Prefix::AddressSizeOverride) {
|
|
m_a32 = !a32;
|
|
m_has_address_size_override_prefix = true;
|
|
continue;
|
|
}
|
|
if (opbyte == Prefix::REPZ || opbyte == Prefix::REPNZ) {
|
|
m_rep_prefix = opbyte;
|
|
continue;
|
|
}
|
|
if (opbyte == Prefix::LOCK) {
|
|
m_has_lock_prefix = true;
|
|
continue;
|
|
}
|
|
auto segment_prefix = to_segment_prefix(opbyte);
|
|
if (segment_prefix.has_value()) {
|
|
m_segment_prefix = (u8)segment_prefix.value();
|
|
continue;
|
|
}
|
|
m_op = opbyte;
|
|
break;
|
|
}
|
|
|
|
if (m_op == 0x0f) {
|
|
m_sub_op = stream.read8();
|
|
m_descriptor = m_o32 ? &s_0f_table32[m_sub_op] : &s_0f_table16[m_sub_op];
|
|
} else {
|
|
m_descriptor = m_o32 ? &s_table32[m_op] : &s_table16[m_op];
|
|
}
|
|
|
|
if (m_descriptor->has_rm) {
|
|
// Consume ModR/M (may include SIB and displacement.)
|
|
m_modrm.decode(stream, m_a32);
|
|
m_register_index = (m_modrm.m_rm >> 3) & 7;
|
|
} else {
|
|
if (has_sub_op())
|
|
m_register_index = m_sub_op & 7;
|
|
else
|
|
m_register_index = m_op & 7;
|
|
}
|
|
|
|
bool has_slash = m_descriptor->format == MultibyteWithSlash;
|
|
if (has_slash) {
|
|
m_descriptor = &m_descriptor->slashes[slash()];
|
|
if ((rm() & 0xc0) == 0xc0 && m_descriptor->slashes)
|
|
m_descriptor = &m_descriptor->slashes[rm() & 7];
|
|
}
|
|
|
|
if (!m_descriptor->mnemonic) {
|
|
if (has_sub_op()) {
|
|
if (has_slash)
|
|
fprintf(stderr, "Instruction %02X %02X /%u not understood\n", m_op, m_sub_op, slash());
|
|
else
|
|
fprintf(stderr, "Instruction %02X %02X not understood\n", m_op, m_sub_op);
|
|
} else {
|
|
if (has_slash)
|
|
fprintf(stderr, "Instruction %02X /%u not understood\n", m_op, slash());
|
|
else
|
|
fprintf(stderr, "Instruction %02X not understood\n", m_op);
|
|
}
|
|
m_descriptor = nullptr;
|
|
return;
|
|
}
|
|
|
|
auto imm1_bytes = m_descriptor->imm1_bytes_for_address_size(m_a32);
|
|
auto imm2_bytes = m_descriptor->imm2_bytes_for_address_size(m_a32);
|
|
|
|
// Consume immediates if present.
|
|
switch (imm2_bytes) {
|
|
case 1:
|
|
m_imm2 = stream.read8();
|
|
break;
|
|
case 2:
|
|
m_imm2 = stream.read16();
|
|
break;
|
|
case 4:
|
|
m_imm2 = stream.read32();
|
|
break;
|
|
default:
|
|
ASSERT(imm2_bytes == 0);
|
|
break;
|
|
}
|
|
|
|
switch (imm1_bytes) {
|
|
case 1:
|
|
m_imm1 = stream.read8();
|
|
break;
|
|
case 2:
|
|
m_imm1 = stream.read16();
|
|
break;
|
|
case 4:
|
|
m_imm1 = stream.read32();
|
|
break;
|
|
default:
|
|
ASSERT(imm1_bytes == 0);
|
|
break;
|
|
}
|
|
|
|
m_extra_bytes = prefix_bytes + imm1_bytes + imm2_bytes;
|
|
|
|
#ifdef DISALLOW_INVALID_LOCK_PREFIX
|
|
if (m_has_lock_prefix && !m_descriptor->lock_prefix_allowed) {
|
|
fprintf(stderr, "Instruction not allowed with LOCK prefix, this will raise #UD\n");
|
|
m_descriptor = nullptr;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
template<typename InstructionStreamType>
|
|
ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stream, bool a32)
|
|
{
|
|
m_rm = stream.read8();
|
|
|
|
if (a32) {
|
|
decode32(stream);
|
|
switch (m_displacement_bytes) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
m_displacement32 = sign_extended_to<u32>(stream.read8());
|
|
break;
|
|
case 4:
|
|
m_displacement32 = stream.read32();
|
|
break;
|
|
default:
|
|
ASSERT_NOT_REACHED();
|
|
break;
|
|
}
|
|
} else {
|
|
decode16(stream);
|
|
switch (m_displacement_bytes) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
m_displacement16 = sign_extended_to<u16>(stream.read8());
|
|
break;
|
|
case 2:
|
|
m_displacement16 = stream.read16();
|
|
break;
|
|
default:
|
|
ASSERT_NOT_REACHED();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
template<typename InstructionStreamType>
|
|
ALWAYS_INLINE void MemoryOrRegisterReference::decode16(InstructionStreamType&)
|
|
{
|
|
switch (m_rm & 0xc0) {
|
|
case 0:
|
|
if ((m_rm & 0x07) == 6)
|
|
m_displacement_bytes = 2;
|
|
else
|
|
ASSERT(m_displacement_bytes == 0);
|
|
break;
|
|
case 0x40:
|
|
m_displacement_bytes = 1;
|
|
break;
|
|
case 0x80:
|
|
m_displacement_bytes = 2;
|
|
break;
|
|
case 0xc0:
|
|
m_register_index = m_rm & 7;
|
|
break;
|
|
}
|
|
}
|
|
|
|
template<typename InstructionStreamType>
|
|
ALWAYS_INLINE void MemoryOrRegisterReference::decode32(InstructionStreamType& stream)
|
|
{
|
|
switch (m_rm & 0xc0) {
|
|
case 0:
|
|
if ((m_rm & 0x07) == 5)
|
|
m_displacement_bytes = 4;
|
|
break;
|
|
case 0x40:
|
|
m_displacement_bytes = 1;
|
|
break;
|
|
case 0x80:
|
|
m_displacement_bytes = 4;
|
|
break;
|
|
case 0xc0:
|
|
m_register_index = m_rm & 7;
|
|
return;
|
|
}
|
|
|
|
m_has_sib = (m_rm & 0x07) == 4;
|
|
if (m_has_sib) {
|
|
m_sib = stream.read8();
|
|
if ((m_sib & 0x07) == 5) {
|
|
switch ((m_rm >> 6) & 0x03) {
|
|
case 0:
|
|
m_displacement_bytes = 4;
|
|
break;
|
|
case 1:
|
|
m_displacement_bytes = 1;
|
|
break;
|
|
case 2:
|
|
m_displacement_bytes = 4;
|
|
break;
|
|
default:
|
|
ASSERT_NOT_REACHED();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
template<typename CPU>
|
|
ALWAYS_INLINE LogicalAddress MemoryOrRegisterReference::resolve(const CPU& cpu, const Instruction& insn)
|
|
{
|
|
if (insn.a32())
|
|
return resolve32(cpu, insn.segment_prefix());
|
|
return resolve16(cpu, insn.segment_prefix());
|
|
}
|
|
|
|
}
|