mirror of
https://github.com/RGBCube/serenity
synced 2025-05-23 18:55:08 +00:00
0d934fc991
Alot of code is shared between i386/i686/x86 and x86_64 and a lot probably will be used for compatability modes. So we start by moving the headers into one Directory. We will probalby be able to move some cpp files aswell.
318 lines
11 KiB
C++
318 lines
11 KiB
C++
/*
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* Copyright (c) 2020, the SerenityOS developers.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <Kernel/Arch/x86/CPU.h>
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#include <Kernel/Arch/x86/SafeMem.h>
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#define CODE_SECTION(section_name) __attribute__((section(section_name)))
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extern "C" u8* start_of_safemem_text;
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extern "C" u8* end_of_safemem_text;
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extern "C" u8* safe_memcpy_ins_1;
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extern "C" u8* safe_memcpy_1_faulted;
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extern "C" u8* safe_memcpy_ins_2;
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extern "C" u8* safe_memcpy_2_faulted;
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extern "C" u8* safe_strnlen_ins;
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extern "C" u8* safe_strnlen_faulted;
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extern "C" u8* safe_memset_ins_1;
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extern "C" u8* safe_memset_1_faulted;
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extern "C" u8* safe_memset_ins_2;
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extern "C" u8* safe_memset_2_faulted;
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extern "C" u8* start_of_safemem_atomic_text;
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extern "C" u8* end_of_safemem_atomic_text;
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extern "C" u8* safe_atomic_fetch_add_relaxed_ins;
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extern "C" u8* safe_atomic_fetch_add_relaxed_faulted;
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extern "C" u8* safe_atomic_exchange_relaxed_ins;
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extern "C" u8* safe_atomic_exchange_relaxed_faulted;
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extern "C" u8* safe_atomic_load_relaxed_ins;
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extern "C" u8* safe_atomic_load_relaxed_faulted;
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extern "C" u8* safe_atomic_store_relaxed_ins;
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extern "C" u8* safe_atomic_store_relaxed_faulted;
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extern "C" u8* safe_atomic_compare_exchange_relaxed_ins;
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extern "C" u8* safe_atomic_compare_exchange_relaxed_faulted;
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namespace Kernel {
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CODE_SECTION(".text.safemem")
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bool safe_memcpy(void* dest_ptr, const void* src_ptr, size_t n, void*& fault_at)
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{
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fault_at = nullptr;
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size_t dest = (size_t)dest_ptr;
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size_t src = (size_t)src_ptr;
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size_t remainder;
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// FIXME: Support starting at an unaligned address.
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if (!(dest & 0x3) && !(src & 0x3) && n >= 12) {
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size_t size_ts = n / sizeof(size_t);
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asm volatile(
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"safe_memcpy_ins_1: \n"
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"rep movsl \n"
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"safe_memcpy_1_faulted: \n" // handle_safe_access_fault() set edx to the fault address!
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: "=S"(src),
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"=D"(dest),
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"=c"(remainder),
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[fault_at] "=d"(fault_at)
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: "S"(src),
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"D"(dest),
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"c"(size_ts)
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: "memory");
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if (remainder != 0)
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return false; // fault_at is already set!
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n -= size_ts * sizeof(size_t);
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if (n == 0) {
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fault_at = nullptr;
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return true;
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}
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}
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asm volatile(
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"safe_memcpy_ins_2: \n"
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"rep movsb \n"
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"safe_memcpy_2_faulted: \n" // handle_safe_access_fault() set edx to the fault address!
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: "=c"(remainder),
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[fault_at] "=d"(fault_at)
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: "S"(src),
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"D"(dest),
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"c"(n)
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: "memory");
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if (remainder != 0)
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return false; // fault_at is already set!
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fault_at = nullptr;
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return true;
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}
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CODE_SECTION(".text.safemem")
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ssize_t safe_strnlen(const char* str, size_t max_n, void*& fault_at)
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{
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ssize_t count = 0;
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fault_at = nullptr;
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asm volatile(
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"1: \n"
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"test %[max_n], %[max_n] \n"
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"je 2f \n"
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"dec %[max_n] \n"
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"safe_strnlen_ins: \n"
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"cmpb $0,(%[str], %[count], 1) \n"
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"je 2f \n"
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"inc %[count] \n"
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"jmp 1b \n"
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"safe_strnlen_faulted: \n" // handle_safe_access_fault() set edx to the fault address!
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"xor %[count_on_error], %[count_on_error] \n"
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"dec %[count_on_error] \n" // return -1 on fault
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"2:"
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: [count_on_error] "=c"(count),
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[fault_at] "=d"(fault_at)
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: [str] "b"(str),
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[count] "c"(count),
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[max_n] "d"(max_n));
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if (count >= 0)
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fault_at = nullptr;
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return count;
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}
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CODE_SECTION(".text.safemem")
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bool safe_memset(void* dest_ptr, int c, size_t n, void*& fault_at)
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{
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fault_at = nullptr;
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size_t dest = (size_t)dest_ptr;
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size_t remainder;
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// FIXME: Support starting at an unaligned address.
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if (!(dest & 0x3) && n >= 12) {
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size_t size_ts = n / sizeof(size_t);
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size_t expanded_c = (u8)c;
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expanded_c |= expanded_c << 8;
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expanded_c |= expanded_c << 16;
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asm volatile(
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"safe_memset_ins_1: \n"
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"rep stosl \n"
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"safe_memset_1_faulted: \n" // handle_safe_access_fault() set edx to the fault address!
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: "=D"(dest),
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"=c"(remainder),
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[fault_at] "=d"(fault_at)
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: "D"(dest),
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"a"(expanded_c),
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"c"(size_ts)
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: "memory");
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if (remainder != 0)
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return false; // fault_at is already set!
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n -= size_ts * sizeof(size_t);
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if (remainder == 0) {
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fault_at = nullptr;
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return true;
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}
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}
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asm volatile(
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"safe_memset_ins_2: \n"
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"rep stosb \n"
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"safe_memset_2_faulted: \n" // handle_safe_access_fault() set edx to the fault address!
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: "=D"(dest),
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"=c"(remainder),
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[fault_at] "=d"(fault_at)
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: "D"(dest),
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"c"(n),
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"a"(c)
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: "memory");
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if (remainder != 0)
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return false; // fault_at is already set!
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fault_at = nullptr;
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return true;
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}
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CODE_SECTION(".text.safemem.atomic")
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Optional<u32> safe_atomic_fetch_add_relaxed(volatile u32* var, u32 val)
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{
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u32 result;
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bool error;
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asm volatile(
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"xor %[error], %[error] \n"
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"safe_atomic_fetch_add_relaxed_ins: \n"
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"lock xadd %[result], %[var] \n"
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"safe_atomic_fetch_add_relaxed_faulted: \n"
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: [error] "=d"(error), [result] "=a"(result), [var] "=m"(*var)
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: [val] "a"(val)
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: "memory");
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if (error)
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return {};
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return result;
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}
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CODE_SECTION(".text.safemem.atomic")
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Optional<u32> safe_atomic_exchange_relaxed(volatile u32* var, u32 val)
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{
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u32 result;
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bool error;
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asm volatile(
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"xor %[error], %[error] \n"
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"safe_atomic_exchange_relaxed_ins: \n"
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"xchg %[val], %[var] \n"
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"safe_atomic_exchange_relaxed_faulted: \n"
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: [error] "=d"(error), "=a"(result), [var] "=m"(*var)
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: [val] "a"(val)
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: "memory");
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if (error)
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return {};
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return result;
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}
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CODE_SECTION(".text.safemem.atomic")
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Optional<u32> safe_atomic_load_relaxed(volatile u32* var)
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{
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u32 result;
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bool error;
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asm volatile(
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"xor %[error], %[error] \n"
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"safe_atomic_load_relaxed_ins: \n"
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"mov (%[var]), %[result] \n"
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"safe_atomic_load_relaxed_faulted: \n"
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: [error] "=d"(error), [result] "=c"(result)
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: [var] "b"(var)
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: "memory");
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if (error)
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return {};
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return result;
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}
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CODE_SECTION(".text.safemem.atomic")
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bool safe_atomic_store_relaxed(volatile u32* var, u32 val)
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{
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bool error;
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asm volatile(
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"xor %[error], %[error] \n"
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"safe_atomic_store_relaxed_ins: \n"
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"xchg %[val], %[var] \n"
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"safe_atomic_store_relaxed_faulted: \n"
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: [error] "=d"(error), [var] "=m"(*var)
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: [val] "r"(val)
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: "memory");
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return !error;
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}
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CODE_SECTION(".text.safemem.atomic")
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Optional<bool> safe_atomic_compare_exchange_relaxed(volatile u32* var, u32& expected, u32 val)
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{
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// NOTE: accessing expected is NOT protected as it should always point
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// to a valid location in kernel memory!
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bool error;
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bool did_exchange;
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asm volatile(
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"xor %[error], %[error] \n"
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"safe_atomic_compare_exchange_relaxed_ins: \n"
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"lock cmpxchg %[val], %[var] \n"
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"safe_atomic_compare_exchange_relaxed_faulted: \n"
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: [error] "=d"(error), "=a"(expected), [var] "=m"(*var), "=@ccz"(did_exchange)
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: "a"(expected), [val] "b"(val)
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: "memory");
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if (error)
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return {};
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return did_exchange;
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}
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bool handle_safe_access_fault(RegisterState& regs, u32 fault_address)
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{
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if (regs.eip >= (FlatPtr)&start_of_safemem_text && regs.eip < (FlatPtr)&end_of_safemem_text) {
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// If we detect that the fault happened in safe_memcpy() safe_strnlen(),
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// or safe_memset() then resume at the appropriate _faulted label
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if (regs.eip == (FlatPtr)&safe_memcpy_ins_1)
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regs.eip = (FlatPtr)&safe_memcpy_1_faulted;
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else if (regs.eip == (FlatPtr)&safe_memcpy_ins_2)
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regs.eip = (FlatPtr)&safe_memcpy_2_faulted;
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else if (regs.eip == (FlatPtr)&safe_strnlen_ins)
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regs.eip = (FlatPtr)&safe_strnlen_faulted;
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else if (regs.eip == (FlatPtr)&safe_memset_ins_1)
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regs.eip = (FlatPtr)&safe_memset_1_faulted;
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else if (regs.eip == (FlatPtr)&safe_memset_ins_2)
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regs.eip = (FlatPtr)&safe_memset_2_faulted;
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else
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return false;
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regs.edx = fault_address;
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return true;
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}
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if (regs.eip >= (FlatPtr)&start_of_safemem_atomic_text && regs.eip < (FlatPtr)&end_of_safemem_atomic_text) {
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// If we detect that a fault happened in one of the atomic safe_
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// functions, resume at the appropriate _faulted label and set
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// the edx register to 1 to indicate an error
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if (regs.eip == (FlatPtr)&safe_atomic_fetch_add_relaxed_ins)
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regs.eip = (FlatPtr)&safe_atomic_fetch_add_relaxed_faulted;
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else if (regs.eip == (FlatPtr)&safe_atomic_exchange_relaxed_ins)
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regs.eip = (FlatPtr)&safe_atomic_exchange_relaxed_faulted;
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else if (regs.eip == (FlatPtr)&safe_atomic_load_relaxed_ins)
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regs.eip = (FlatPtr)&safe_atomic_load_relaxed_faulted;
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else if (regs.eip == (FlatPtr)&safe_atomic_store_relaxed_ins)
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regs.eip = (FlatPtr)&safe_atomic_store_relaxed_faulted;
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else if (regs.eip == (FlatPtr)&safe_atomic_compare_exchange_relaxed_ins)
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regs.eip = (FlatPtr)&safe_atomic_compare_exchange_relaxed_faulted;
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else
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return false;
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regs.edx = 1;
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return true;
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}
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return false;
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}
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}
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