mirror of
https://github.com/RGBCube/serenity
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6e46e21c42
This allows us to enable Write-Combine on e.g. framebuffers, significantly improving performance on bare metal. To keep things simple we right now only use one of up to three bits (bit 7 in the PTE), which maps to the PA4 entry in the PAT MSR, which we set to the Write-Combine mode on each CPU at boot time.
64 lines
1.5 KiB
C++
64 lines
1.5 KiB
C++
/*
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* Copyright (c) 2018-2021, Andreas Kling <kling@serenityos.org>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Types.h>
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#include <AK/Platform.h>
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VALIDATE_IS_X86()
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namespace Kernel {
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class CPUID {
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public:
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explicit CPUID(u32 function, u32 ecx = 0) { asm volatile("cpuid"
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: "=a"(m_eax), "=b"(m_ebx), "=c"(m_ecx), "=d"(m_edx)
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: "a"(function), "c"(ecx)); }
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u32 eax() const { return m_eax; }
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u32 ebx() const { return m_ebx; }
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u32 ecx() const { return m_ecx; }
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u32 edx() const { return m_edx; }
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private:
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u32 m_eax { 0xffffffff };
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u32 m_ebx { 0xffffffff };
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u32 m_ecx { 0xffffffff };
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u32 m_edx { 0xffffffff };
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};
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// FIXME: This can't hold every CPU feature as-is.
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enum class CPUFeature : u32 {
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NX = (1 << 0),
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PAE = (1 << 1),
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PGE = (1 << 2),
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RDRAND = (1 << 3),
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RDSEED = (1 << 4),
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SMAP = (1 << 5),
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SMEP = (1 << 6),
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SSE = (1 << 7),
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TSC = (1 << 8),
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RDTSCP = (1 << 9),
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CONSTANT_TSC = (1 << 10),
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NONSTOP_TSC = (1 << 11),
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UMIP = (1 << 12),
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SEP = (1 << 13),
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SYSCALL = (1 << 14),
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MMX = (1 << 15),
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SSE2 = (1 << 16),
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SSE3 = (1 << 17),
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SSSE3 = (1 << 18),
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SSE4_1 = (1 << 19),
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SSE4_2 = (1 << 20),
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XSAVE = (1 << 21),
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AVX = (1 << 22),
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FXSR = (1 << 23),
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LM = (1 << 24),
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HYPERVISOR = (1 << 25),
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PAT = (1 << 26),
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};
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}
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