mirror of
https://github.com/RGBCube/serenity
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94ca55cefd
As suggested by Joshua, this commit adds the 2-clause BSD license as a comment block to the top of every source file. For the first pass, I've just added myself for simplicity. I encourage everyone to add themselves as copyright holders of any file they've added or modified in some significant way. If I've added myself in error somewhere, feel free to replace it with the appropriate copyright holder instead. Going forward, all new source files should include a license header.
140 lines
3.7 KiB
C++
140 lines
3.7 KiB
C++
/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <AK/Assertions.h>
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#include <AK/Types.h>
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#include <Kernel/Arch/i386/CPU.h>
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#include <Kernel/Arch/i386/PIC.h>
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#include <Kernel/IO.h>
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// The slave 8259 is connected to the master's IRQ2 line.
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// This is really only to enhance clarity.
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#define SLAVE_INDEX 2
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#define PIC0_CTL 0x20
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#define PIC0_CMD 0x21
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#define PIC1_CTL 0xA0
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#define PIC1_CMD 0xA1
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#ifdef DEBUG_PIC
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static bool initialized;
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#endif
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namespace PIC {
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void disable(u8 irq)
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{
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InterruptDisabler disabler;
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u8 imr;
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if (irq & 8) {
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imr = IO::in8(PIC1_CMD);
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imr |= 1 << (irq - 8);
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IO::out8(PIC1_CMD, imr);
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} else {
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imr = IO::in8(PIC0_CMD);
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imr |= 1 << irq;
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IO::out8(PIC0_CMD, imr);
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}
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}
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void enable(u8 irq)
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{
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InterruptDisabler disabler;
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u8 imr;
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if (irq & 8) {
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imr = IO::in8(PIC1_CMD);
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imr &= ~(1 << (irq - 8));
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IO::out8(PIC1_CMD, imr);
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} else {
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imr = IO::in8(PIC0_CMD);
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imr &= ~(1 << irq);
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IO::out8(PIC0_CMD, imr);
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}
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}
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void eoi(u8 irq)
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{
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if (irq & 8)
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IO::out8(PIC1_CTL, 0x20);
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IO::out8(PIC0_CTL, 0x20);
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}
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void initialize()
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{
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#ifdef DEBUG_PIC
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ASSERT(!initialized);
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#endif
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/* ICW1 (edge triggered mode, cascading controllers, expect ICW4) */
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IO::out8(PIC0_CTL, 0x11);
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IO::out8(PIC1_CTL, 0x11);
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/* ICW2 (upper 5 bits specify ISR indices, lower 3 idunno) */
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IO::out8(PIC0_CMD, IRQ_VECTOR_BASE);
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IO::out8(PIC1_CMD, IRQ_VECTOR_BASE + 0x08);
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/* ICW3 (configure master/slave relationship) */
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IO::out8(PIC0_CMD, 1 << SLAVE_INDEX);
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IO::out8(PIC1_CMD, SLAVE_INDEX);
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/* ICW4 (set x86 mode) */
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IO::out8(PIC0_CMD, 0x01);
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IO::out8(PIC1_CMD, 0x01);
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// Mask -- start out with all IRQs disabled.
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IO::out8(PIC0_CMD, 0xff);
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IO::out8(PIC1_CMD, 0xff);
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// ...except IRQ2, since that's needed for the master to let through slave interrupts.
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enable(2);
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kprintf("PIC(i8259): cascading mode, vectors 0x%b-0x%b\n", IRQ_VECTOR_BASE, IRQ_VECTOR_BASE + 0x08);
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#ifdef DEBUG_PIC
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initialized = true;
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#endif
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}
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u16 get_isr()
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{
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IO::out8(PIC0_CTL, 0x0b);
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IO::out8(PIC1_CTL, 0x0b);
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u8 isr0 = IO::in8(PIC0_CTL);
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u8 isr1 = IO::in8(PIC1_CTL);
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return (isr1 << 8) | isr0;
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}
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u16 get_irr()
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{
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IO::out8(PIC0_CTL, 0x0a);
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IO::out8(PIC1_CTL, 0x0a);
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u8 irr0 = IO::in8(PIC0_CTL);
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u8 irr1 = IO::in8(PIC1_CTL);
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return (irr1 << 8) | irr0;
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}
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}
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