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https://github.com/RGBCube/serenity
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Two classes are added - HostBridge and MemoryBackedHostBridge, which both derive from HostController class. This allows the kernel to map different busses from different PCI domains in the same time. Each HostController implementation doesn't take the Address object to address PCI devices but instead we take distinct numbers of the PCI bus, device and function as it allows us to specify arbitrary PCI domains in the Address structure and still to get the correct PCI devices. This also matches the hardware behavior of PCI domains - the host bridge merely takes memory operations or IO operations and translates them to addressing of three components - PCI bus, device and function. These changes also greatly simplify how enumeration of Host Bridges work now - scanning of the hardware depends on what the Host bridges can do for us, so in case we have multiple host bridges that expose a memory mapped region or IO ports to access PCI configuration space, we simply let the code of the host bridge to figure out how to fetch data for us. Another semantical change is that a PCI domain structure is no longer attached to a PhysicalAddress, so even in the case that the machine doesn't implement PCI domains, we still treat that machine to contain 1 PCI domain to treat that one host bridge in the same way, like with a machine with one or more PCI domains.
318 lines
8.6 KiB
C++
318 lines
8.6 KiB
C++
/*
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* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Badge.h>
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#include <AK/DistinctNumeric.h>
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#include <AK/Function.h>
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#include <AK/Types.h>
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#include <AK/Vector.h>
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#include <Kernel/Debug.h>
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#include <Kernel/PhysicalAddress.h>
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namespace Kernel {
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namespace PCI {
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enum class HeaderType {
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Device = 0,
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Bridge = 1,
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};
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enum class RegisterOffset {
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VENDOR_ID = 0x00, // word
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DEVICE_ID = 0x02, // word
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COMMAND = 0x04, // word
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STATUS = 0x06, // word
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REVISION_ID = 0x08, // byte
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PROG_IF = 0x09, // byte
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SUBCLASS = 0x0a, // byte
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CLASS = 0x0b, // byte
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CACHE_LINE_SIZE = 0x0c, // byte
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LATENCY_TIMER = 0x0d, // byte
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HEADER_TYPE = 0x0e, // byte
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BIST = 0x0f, // byte
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BAR0 = 0x10, // u32
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BAR1 = 0x14, // u32
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BAR2 = 0x18, // u32
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SECONDARY_BUS = 0x19, // byte
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BAR3 = 0x1C, // u32
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BAR4 = 0x20, // u32
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BAR5 = 0x24, // u32
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SUBSYSTEM_VENDOR_ID = 0x2C, // u16
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SUBSYSTEM_ID = 0x2E, // u16
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CAPABILITIES_POINTER = 0x34, // u8
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INTERRUPT_LINE = 0x3C, // byte
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INTERRUPT_PIN = 0x3D, // byte
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};
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enum class Limits {
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MaxDevicesPerBus = 32,
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MaxBusesPerDomain = 256,
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MaxFunctionsPerDevice = 8,
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};
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static constexpr u16 address_port = 0xcf8;
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static constexpr u16 value_port = 0xcfc;
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static constexpr size_t mmio_device_space_size = 4096;
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static constexpr u16 none_value = 0xffff;
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static constexpr size_t memory_range_per_bus = mmio_device_space_size * to_underlying(Limits::MaxFunctionsPerDevice) * to_underlying(Limits::MaxDevicesPerBus);
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// Taken from https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_11__v24_Jan_2019.pdf
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enum class ClassID {
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MassStorage = 0x1,
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Multimedia = 0x4,
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Bridge = 0x6,
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};
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namespace MassStorage {
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enum class SubclassID {
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IDEController = 0x1,
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SATAController = 0x6,
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NVMeController = 0x8,
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};
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enum class SATAProgIF {
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AHCI = 0x1,
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};
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}
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namespace Multimedia {
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enum class SubclassID {
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AudioController = 0x1,
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};
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}
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namespace Bridge {
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enum class SubclassID {
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PCI_TO_PCI = 0x4,
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};
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}
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TYPEDEF_DISTINCT_ORDERED_ID(u8, CapabilityID);
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namespace Capabilities {
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enum ID {
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Null = 0x0,
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MSI = 0x5,
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VendorSpecific = 0x9,
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MSIX = 0x11,
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};
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}
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struct HardwareID {
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u16 vendor_id { 0 };
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u16 device_id { 0 };
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bool is_null() const { return !vendor_id && !device_id; }
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bool operator==(const HardwareID& other) const
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{
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return vendor_id == other.vendor_id && device_id == other.device_id;
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}
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bool operator!=(const HardwareID& other) const
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{
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return vendor_id != other.vendor_id || device_id != other.device_id;
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}
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};
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class Domain {
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public:
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Domain() = delete;
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Domain(u32 domain_number, u8 start_bus, u8 end_bus)
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: m_domain_number(domain_number)
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, m_start_bus(start_bus)
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, m_end_bus(end_bus)
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{
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}
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u8 start_bus() const { return m_start_bus; }
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u8 end_bus() const { return m_end_bus; }
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u32 domain_number() const { return m_domain_number; }
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private:
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u32 m_domain_number;
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u8 m_start_bus;
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u8 m_end_bus;
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};
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struct Address {
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public:
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Address() = default;
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Address(u32 domain)
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: m_domain(domain)
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, m_bus(0)
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, m_device(0)
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, m_function(0)
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{
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}
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Address(u32 domain, u8 bus, u8 device, u8 function)
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: m_domain(domain)
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, m_bus(bus)
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, m_device(device)
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, m_function(function)
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{
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}
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Address(const Address& address) = default;
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bool is_null() const { return !m_bus && !m_device && !m_function; }
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operator bool() const { return !is_null(); }
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// Disable default implementations that would use surprising integer promotion.
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bool operator<=(const Address&) const = delete;
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bool operator>=(const Address&) const = delete;
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bool operator<(const Address&) const = delete;
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bool operator>(const Address&) const = delete;
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bool operator==(const Address& other) const
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{
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if (this == &other)
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return true;
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return m_domain == other.m_domain && m_bus == other.m_bus && m_device == other.m_device && m_function == other.m_function;
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}
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bool operator!=(const Address& other) const
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{
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return !(*this == other);
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}
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u16 domain() const { return m_domain; }
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u8 bus() const { return m_bus; }
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u8 device() const { return m_device; }
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u8 function() const { return m_function; }
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private:
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u32 m_domain { 0 };
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u8 m_bus { 0 };
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u8 m_device { 0 };
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u8 m_function { 0 };
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};
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class Capability {
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public:
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Capability(const Address& address, u8 id, u8 ptr)
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: m_address(address)
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, m_id(id)
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, m_ptr(ptr)
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{
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}
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CapabilityID id() const { return m_id; }
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u8 read8(u32) const;
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u16 read16(u32) const;
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u32 read32(u32) const;
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void write8(u32, u8);
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void write16(u32, u16);
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void write32(u32, u32);
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private:
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Address m_address;
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const CapabilityID m_id;
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const u8 m_ptr;
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};
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TYPEDEF_DISTINCT_ORDERED_ID(u8, ClassCode);
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TYPEDEF_DISTINCT_ORDERED_ID(u8, SubclassCode);
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TYPEDEF_DISTINCT_ORDERED_ID(u8, ProgrammingInterface);
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TYPEDEF_DISTINCT_ORDERED_ID(u8, RevisionID);
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TYPEDEF_DISTINCT_ORDERED_ID(u16, SubsystemID);
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TYPEDEF_DISTINCT_ORDERED_ID(u16, SubsystemVendorID);
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TYPEDEF_DISTINCT_ORDERED_ID(u8, InterruptLine);
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TYPEDEF_DISTINCT_ORDERED_ID(u8, InterruptPin);
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class Access;
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class DeviceIdentifier {
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public:
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DeviceIdentifier(Address address, HardwareID hardware_id, RevisionID revision_id, ClassCode class_code, SubclassCode subclass_code, ProgrammingInterface prog_if, SubsystemID subsystem_id, SubsystemVendorID subsystem_vendor_id, InterruptLine interrupt_line, InterruptPin interrupt_pin, Vector<Capability> const& capabilities)
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: m_address(address)
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, m_hardware_id(hardware_id)
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, m_revision_id(revision_id)
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, m_class_code(class_code)
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, m_subclass_code(subclass_code)
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, m_prog_if(prog_if)
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, m_subsystem_id(subsystem_id)
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, m_subsystem_vendor_id(subsystem_vendor_id)
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, m_interrupt_line(interrupt_line)
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, m_interrupt_pin(interrupt_pin)
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, m_capabilities(capabilities)
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{
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if constexpr (PCI_DEBUG) {
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for (const auto& capability : capabilities)
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dbgln("{} has capability {}", address, capability.id());
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}
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}
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Vector<Capability> const& capabilities() const { return m_capabilities; }
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HardwareID const& hardware_id() const { return m_hardware_id; }
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Address const& address() const { return m_address; }
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RevisionID revision_id() const { return m_revision_id; }
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ClassCode class_code() const { return m_class_code; }
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SubclassCode subclass_code() const { return m_subclass_code; }
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ProgrammingInterface prog_if() const { return m_prog_if; }
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SubsystemID subsystem_id() const { return m_subsystem_id; }
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SubsystemVendorID subsystem_vendor_id() const { return m_subsystem_vendor_id; }
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InterruptLine interrupt_line() const { return m_interrupt_line; }
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InterruptPin interrupt_pin() const { return m_interrupt_pin; }
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void apply_subclass_code_change(Badge<Access>, SubclassCode new_subclass)
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{
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m_subclass_code = new_subclass;
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}
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void apply_prog_if_change(Badge<Access>, ProgrammingInterface new_progif)
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{
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m_prog_if = new_progif;
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}
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private:
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Address m_address;
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HardwareID m_hardware_id;
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RevisionID m_revision_id;
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ClassCode m_class_code;
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SubclassCode m_subclass_code;
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ProgrammingInterface m_prog_if;
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SubsystemID m_subsystem_id;
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SubsystemVendorID m_subsystem_vendor_id;
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InterruptLine m_interrupt_line;
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InterruptPin m_interrupt_pin;
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Vector<Capability> m_capabilities;
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};
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class Domain;
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class Device;
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}
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}
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template<>
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struct AK::Formatter<Kernel::PCI::Address> : Formatter<FormatString> {
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ErrorOr<void> format(FormatBuilder& builder, Kernel::PCI::Address value)
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{
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return Formatter<FormatString>::format(
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builder,
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"PCI [{:04x}:{:02x}:{:02x}:{:02x}]", value.domain(), value.bus(), value.device(), value.function());
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}
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};
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template<>
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struct AK::Formatter<Kernel::PCI::HardwareID> : Formatter<FormatString> {
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ErrorOr<void> format(FormatBuilder& builder, Kernel::PCI::HardwareID value)
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{
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return Formatter<FormatString>::format(
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builder,
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"PCI::HardwareID [{:04x}:{:04x}]", value.vendor_id, value.device_id);
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}
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};
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