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https://github.com/RGBCube/serenity
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There are now 2 separate classes for almost the same object type: - EnumerableDeviceIdentifier, which is used in the enumeration code for all PCI host controller classes. This is allowed to be moved and copied, as it doesn't support ref-counting. - DeviceIdentifier, which inherits from EnumerableDeviceIdentifier. This class uses ref-counting, and is not allowed to be copied. It has a spinlock member in its structure to allow safely executing complicated IO sequences on a PCI device and its space configuration. There's a static method that allows a quick conversion from EnumerableDeviceIdentifier to DeviceIdentifier while creating a NonnullRefPtr out of it. The reason for doing this is for the sake of integrity and reliablity of the system in 2 places: - Ensure that "complicated" tasks that rely on manipulating PCI device registers are done in a safe manner. For example, determining a PCI BAR space size requires multiple read and writes to the same register, and if another CPU tries to do something else with our selected register, then the result will be a catastrophe. - Allow the PCI API to have a united form around a shared object which actually holds much more data than the PCI::Address structure. This is fundamental if we want to do certain types of optimizations, and be able to support more features of the PCI bus in the foreseeable future. This patch already has several implications: - All PCI::Device(s) hold a reference to a DeviceIdentifier structure being given originally from the PCI::Access singleton. This means that all instances of DeviceIdentifier structures are located in one place, and all references are pointing to that location. This ensures that locking the operation spinlock will take effect in all the appropriate places. - We no longer support adding PCI host controllers and then immediately allow for enumerating it with a lambda function. It was found that this method is extremely broken and too much complicated to work reliably with the new paradigm being introduced in this patch. This means that for Volume Management Devices (Intel VMD devices), we simply first enumerate the PCI bus for such devices in the storage code, and if we find a device, we attach it in the PCI::Access method which will scan for devices behind that bridge and will add new DeviceIdentifier(s) objects to its internal Vector. Afterwards, we just continue as usual with scanning for actual storage controllers, so we will find a corresponding NVMe controllers if there were any behind that VMD bridge.
160 lines
5.2 KiB
C++
160 lines
5.2 KiB
C++
/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/ByteReader.h>
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#include <AK/Platform.h>
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#include <AK/Types.h>
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#if ARCH(X86_64)
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# include <Kernel/Arch/x86_64/IO.h>
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#endif
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#include <Kernel/Bus/PCI/Definitions.h>
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#include <Kernel/Memory/TypedMapping.h>
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#include <Kernel/PhysicalAddress.h>
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namespace Kernel {
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class IOWindow {
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public:
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enum class SpaceType {
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#if ARCH(X86_64)
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IO,
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#endif
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Memory,
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};
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SpaceType space_type() const { return m_space_type; }
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template<typename V>
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void write();
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#if ARCH(X86_64)
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static ErrorOr<NonnullOwnPtr<IOWindow>> create_for_io_space(IOAddress, u64 space_length);
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#endif
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static ErrorOr<NonnullOwnPtr<IOWindow>> create_for_pci_device_bar(PCI::DeviceIdentifier const&, PCI::HeaderType0BaseRegister, u64 space_length);
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static ErrorOr<NonnullOwnPtr<IOWindow>> create_for_pci_device_bar(PCI::DeviceIdentifier const&, PCI::HeaderType0BaseRegister);
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ErrorOr<NonnullOwnPtr<IOWindow>> create_from_io_window_with_offset(u64 offset, u64 space_length);
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ErrorOr<NonnullOwnPtr<IOWindow>> create_from_io_window_with_offset(u64 offset);
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bool is_access_valid(u64 offset, size_t byte_size_access) const;
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u8 read8(u64 offset);
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u16 read16(u64 offset);
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u32 read32(u64 offset);
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void write8(u64 offset, u8);
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void write16(u64 offset, u16);
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void write32(u64 offset, u32);
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// Note: These methods are useful in exceptional cases where we need to do unaligned
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// access. This mostly happens on emulators and hypervisors (such as VMWare) because they don't enforce aligned access
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// to IO and sometimes even require such access, so we have to use these functions.
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void write32_unaligned(u64 offset, u32);
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u32 read32_unaligned(u64 offset);
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bool operator==(IOWindow const& other) const = delete;
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bool operator!=(IOWindow const& other) const = delete;
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bool operator>(IOWindow const& other) const = delete;
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bool operator>=(IOWindow const& other) const = delete;
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bool operator<(IOWindow const& other) const = delete;
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bool operator<=(IOWindow const& other) const = delete;
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~IOWindow();
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PhysicalAddress as_physical_memory_address() const;
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#if ARCH(X86_64)
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IOAddress as_io_address() const;
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#endif
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private:
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explicit IOWindow(NonnullOwnPtr<Memory::TypedMapping<u8 volatile>>);
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u8 volatile* as_memory_address_pointer();
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#if ARCH(X86_64)
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struct IOAddressData {
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public:
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IOAddressData(u64 address, u64 space_length)
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: m_address(address)
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, m_space_length(space_length)
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{
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}
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u64 address() const { return m_address; }
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u64 space_length() const { return m_space_length; }
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private:
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u64 m_address { 0 };
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u64 m_space_length { 0 };
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};
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explicit IOWindow(NonnullOwnPtr<IOAddressData>);
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#endif
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bool is_access_in_range(u64 offset, size_t byte_size_access) const;
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bool is_access_aligned(u64 offset, size_t byte_size_access) const;
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template<typename T>
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ALWAYS_INLINE void in(u64 start_offset, T& data)
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{
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#if ARCH(X86_64)
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if (m_space_type == SpaceType::IO) {
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data = as_io_address().offset(start_offset).in<T>();
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return;
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}
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#endif
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VERIFY(m_space_type == SpaceType::Memory);
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VERIFY(m_memory_mapped_range);
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// Note: For memory-mapped IO we simply never allow unaligned access as it
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// can cause problems with strict bare metal hardware. For example, some XHCI USB controllers
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// might completely lock up because of an unaligned memory access to their registers.
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VERIFY((start_offset % sizeof(T)) == 0);
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data = *(T volatile*)(as_memory_address_pointer() + start_offset);
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}
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template<typename T>
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ALWAYS_INLINE void out(u64 start_offset, T value)
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{
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#if ARCH(X86_64)
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if (m_space_type == SpaceType::IO) {
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VERIFY(m_io_range);
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as_io_address().offset(start_offset).out<T>(value);
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return;
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}
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#endif
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VERIFY(m_space_type == SpaceType::Memory);
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VERIFY(m_memory_mapped_range);
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// Note: For memory-mapped IO we simply never allow unaligned access as it
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// can cause problems with strict bare metal hardware. For example, some XHCI USB controllers
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// might completely lock up because of an unaligned memory access to their registers.
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VERIFY((start_offset % sizeof(T)) == 0);
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*(T volatile*)(as_memory_address_pointer() + start_offset) = value;
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}
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SpaceType m_space_type { SpaceType::Memory };
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OwnPtr<Memory::TypedMapping<u8 volatile>> m_memory_mapped_range;
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#if ARCH(X86_64)
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OwnPtr<IOAddressData> m_io_range;
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#endif
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};
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}
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template<>
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struct AK::Formatter<Kernel::IOWindow> : AK::Formatter<FormatString> {
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ErrorOr<void> format(FormatBuilder& builder, Kernel::IOWindow const& value)
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{
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#if ARCH(X86_64)
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if (value.space_type() == Kernel::IOWindow::SpaceType::IO)
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return Formatter<FormatString>::format(builder, "{}"sv, value.as_io_address());
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#endif
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VERIFY(value.space_type() == Kernel::IOWindow::SpaceType::Memory);
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return Formatter<FormatString>::format(builder, "Memory {}"sv, value.as_physical_memory_address());
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}
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};
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