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In the real world, graphics hardware tend to have multiple display connectors. However, usually the connectors share one register space but still keeping different PLL timings and display lanes. This new class should represent a group of multiple display connectors working together in the same Intel graphics adapter. This opens an opportunity to abstract the interface so we could support future Intel iGPU generations. This is also a preparation before the driver can support newer devices and utilize their capabilities. The mentioned preparation is applied in a these aspects: 1. The code is splitted into more classes to adjust to future expansion. 2 classes are introduced: IntelDisplayPlane and IntelDisplayTranscoder, so the IntelDisplayPlane controls the plane registers and second class controls the pipeline (transcoder, encoder) registers. On gen4 it's not really useful because there are probably one plane and one encoder to care about, but in future generations, there are likely to be multiple transcoders and planes to accommodate multi head support. 2. The set_edid_bytes method in the DisplayConnector class can now be told to not assume the provided EDID bytes are always invalid. Therefore it can refrain from printing error messages if this flag parameter is true. This is useful for supporting real hardware situation when on boot not all ports are connected to a monitor, which can result in floating bus condition (essentially all the bytes we read are 0xFF). 3. An IntelNativeDisplayConnector could now be set to flag other types of connections such as eDP (embedded DisplayPort), Analog output, etc. This is important because on the Intel gen4 graphics we could assume to have one analog output connector, but on future generations this is very likely to not be the case, as there might be no VGA outputs, but rather only an eDP connector which is converted to VGA by a design choice of the motherboard manufacturer. 4. Add ConnectorIndex to IntelNativeDisplayConnector class - Currently this is used to verify we always handle the correct connector when doing modesetting. Later, it will be used to locate special settings needed when handling connector requests. 5. Prepare to support more types of display planes. For example, the Intel Skylake register set for display planes is a bit different, so let's ensure we can properly support it in the near future.
115 lines
4.2 KiB
C++
115 lines
4.2 KiB
C++
/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/RefPtr.h>
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#include <AK/Try.h>
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#include <Kernel/Graphics/Console/GenericFramebufferConsole.h>
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#include <Kernel/Graphics/Intel/Auxiliary/GMBusConnector.h>
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#include <Kernel/Graphics/Intel/Definitions.h>
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#include <Kernel/Graphics/Intel/NativeDisplayConnector.h>
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#include <Kernel/Graphics/Intel/Plane/DisplayPlane.h>
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#include <Kernel/Graphics/Intel/Transcoder/DisplayTranscoder.h>
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#include <Kernel/Library/LockRefPtr.h>
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#include <Kernel/Memory/TypedMapping.h>
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#include <LibEDID/EDID.h>
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namespace Kernel {
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class IntelNativeGraphicsAdapter;
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class IntelDisplayConnectorGroup : public RefCounted<IntelDisplayConnectorGroup> {
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friend class IntelNativeGraphicsAdapter;
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public:
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enum class Generation {
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Gen4,
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};
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struct MMIORegion {
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enum class BARAssigned {
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BAR0,
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BAR2,
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};
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BARAssigned pci_bar_assigned;
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PhysicalAddress pci_bar_paddr;
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size_t pci_bar_space_length;
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};
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private:
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AK_TYPEDEF_DISTINCT_ORDERED_ID(size_t, RegisterOffset);
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enum class AnalogOutputRegisterOffset {
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AnalogDisplayPort = 0x61100,
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VGADisplayPlaneControl = 0x71400,
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};
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public:
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static ErrorOr<NonnullLockRefPtr<IntelDisplayConnectorGroup>> try_create(Badge<IntelNativeGraphicsAdapter>, Generation, MMIORegion const&, MMIORegion const&);
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ErrorOr<void> set_safe_mode_setting(Badge<IntelNativeDisplayConnector>, IntelNativeDisplayConnector&);
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ErrorOr<void> set_mode_setting(Badge<IntelNativeDisplayConnector>, IntelNativeDisplayConnector&, DisplayConnector::ModeSetting const&);
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private:
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IntelDisplayConnectorGroup(Generation generation, NonnullOwnPtr<GMBusConnector>, NonnullOwnPtr<Memory::Region> registers_region, MMIORegion const&, MMIORegion const&);
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ErrorOr<void> set_mode_setting(IntelNativeDisplayConnector&, DisplayConnector::ModeSetting const&);
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StringView convert_analog_output_register_to_string(AnalogOutputRegisterOffset index) const;
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void write_to_analog_output_register(AnalogOutputRegisterOffset, u32 value);
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u32 read_from_analog_output_register(AnalogOutputRegisterOffset) const;
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u32 read_from_global_generation_register(IntelGraphics::GlobalGenerationRegister index) const;
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void write_to_global_generation_register(IntelGraphics::GlobalGenerationRegister index, u32 value);
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void write_to_general_register(RegisterOffset offset, u32 value);
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u32 read_from_general_register(RegisterOffset offset) const;
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// DisplayConnector initialization related methods
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ErrorOr<void> initialize_connectors();
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ErrorOr<void> initialize_gen4_connectors();
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// General Modesetting methods
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ErrorOr<void> set_gen4_mode_setting(IntelNativeDisplayConnector&, DisplayConnector::ModeSetting const&);
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bool pipe_a_enabled() const;
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bool pipe_b_enabled() const;
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bool set_crt_resolution(DisplayConnector::ModeSetting const&);
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void disable_vga_emulation();
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void enable_vga_plane();
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void disable_dac_output();
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void enable_dac_output();
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void disable_pipe_a();
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void disable_pipe_b();
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void enable_pipe_a();
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bool wait_for_enabled_pipe_a(size_t milliseconds_timeout) const;
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bool wait_for_disabled_pipe_a(size_t milliseconds_timeout) const;
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bool wait_for_disabled_pipe_b(size_t milliseconds_timeout) const;
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Optional<IntelGraphics::PLLSettings> create_pll_settings(u64 target_frequency, u64 reference_clock, IntelGraphics::PLLMaxSettings const&);
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Spinlock<LockRank::None> m_control_lock;
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Spinlock<LockRank::None> m_modeset_lock;
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mutable Spinlock<LockRank::None> m_registers_lock;
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// Note: The linux driver specifies an enum of possible ports and there is only
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// 9 ports (PORT_{A-I}). PORT_TC{1-6} are mapped to PORT_{D-I}.
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Array<LockRefPtr<IntelNativeDisplayConnector>, 9> m_connectors;
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Array<OwnPtr<IntelDisplayTranscoder>, 5> m_transcoders;
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Array<OwnPtr<IntelDisplayPlane>, 3> m_planes;
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const MMIORegion m_mmio_first_region;
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const MMIORegion m_mmio_second_region;
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MMIORegion const& m_assigned_mmio_registers_region;
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const Generation m_generation;
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NonnullOwnPtr<Memory::Region> m_registers_region;
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NonnullOwnPtr<GMBusConnector> m_gmbus_connector;
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};
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}
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