mirror of
https://github.com/RGBCube/serenity
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7c0540a229
This has KString, KBuffer, DoubleBuffer, KBufferBuilder, IOWindow, UserOrKernelBuffer and ScopedCritical classes being moved to the Kernel/Library subdirectory. Also, move the panic and assertions handling code to that directory.
265 lines
12 KiB
C++
265 lines
12 KiB
C++
/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Bus/PCI/Definitions.h>
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#include <Kernel/Library/IOWindow.h>
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namespace Kernel {
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#if ARCH(X86_64)
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ErrorOr<NonnullOwnPtr<IOWindow>> IOWindow::create_for_io_space(IOAddress address, u64 space_length)
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{
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VERIFY(!Checked<u64>::addition_would_overflow(address.get(), space_length));
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auto io_address_range = TRY(adopt_nonnull_own_or_enomem(new (nothrow) IOAddressData(address.get(), space_length)));
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return TRY(adopt_nonnull_own_or_enomem(new (nothrow) IOWindow(move(io_address_range))));
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}
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IOWindow::IOWindow(NonnullOwnPtr<IOAddressData> io_range)
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: m_space_type(SpaceType::IO)
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, m_io_range(move(io_range))
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{
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}
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#endif
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ErrorOr<NonnullOwnPtr<IOWindow>> IOWindow::create_from_io_window_with_offset(u64 offset, u64 space_length)
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{
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#if ARCH(X86_64)
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if (m_space_type == SpaceType::IO) {
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VERIFY(m_io_range);
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if (Checked<u64>::addition_would_overflow(m_io_range->address(), space_length))
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return Error::from_errno(EOVERFLOW);
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auto io_address_range = TRY(adopt_nonnull_own_or_enomem(new (nothrow) IOAddressData(as_io_address().offset(offset).get(), space_length)));
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return TRY(adopt_nonnull_own_or_enomem(new (nothrow) IOWindow(move(io_address_range))));
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}
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#endif
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VERIFY(space_type() == SpaceType::Memory);
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VERIFY(m_memory_mapped_range);
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if (Checked<u64>::addition_would_overflow(m_memory_mapped_range->paddr.get(), offset))
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return Error::from_errno(EOVERFLOW);
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if (Checked<u64>::addition_would_overflow(m_memory_mapped_range->paddr.get() + offset, space_length))
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return Error::from_errno(EOVERFLOW);
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auto memory_mapped_range = TRY(Memory::adopt_new_nonnull_own_typed_mapping<u8 volatile>(m_memory_mapped_range->paddr.offset(offset), space_length, Memory::Region::Access::ReadWrite));
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return TRY(adopt_nonnull_own_or_enomem(new (nothrow) IOWindow(move(memory_mapped_range))));
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}
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ErrorOr<NonnullOwnPtr<IOWindow>> IOWindow::create_from_io_window_with_offset(u64 offset)
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{
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#if ARCH(X86_64)
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if (m_space_type == SpaceType::IO) {
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VERIFY(m_io_range);
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VERIFY(m_io_range->space_length() >= offset);
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return create_from_io_window_with_offset(offset, m_io_range->space_length() - offset);
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}
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#endif
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VERIFY(space_type() == SpaceType::Memory);
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VERIFY(m_memory_mapped_range);
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VERIFY(m_memory_mapped_range->length >= offset);
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return create_from_io_window_with_offset(offset, m_memory_mapped_range->length - offset);
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}
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ErrorOr<NonnullOwnPtr<IOWindow>> IOWindow::create_for_pci_device_bar(PCI::DeviceIdentifier const& pci_device_identifier, PCI::HeaderType0BaseRegister pci_bar, u64 space_length)
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{
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u64 pci_bar_value = PCI::get_BAR(pci_device_identifier, pci_bar);
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auto pci_bar_space_type = PCI::get_BAR_space_type(pci_bar_value);
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if (pci_bar_space_type == PCI::BARSpaceType::Memory64BitSpace) {
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// FIXME: In theory, BAR5 cannot be assigned to 64 bit as it is the last one...
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// however, there might be 64 bit BAR5 for real bare metal hardware, so remove this
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// if it makes a problem.
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if (pci_bar == PCI::HeaderType0BaseRegister::BAR5) {
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return Error::from_errno(EINVAL);
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}
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u64 next_pci_bar_value = PCI::get_BAR(pci_device_identifier, static_cast<PCI::HeaderType0BaseRegister>(to_underlying(pci_bar) + 1));
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pci_bar_value |= next_pci_bar_value << 32;
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}
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auto pci_bar_space_size = PCI::get_BAR_space_size(pci_device_identifier, pci_bar);
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if (pci_bar_space_size < space_length)
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return Error::from_errno(EIO);
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if (pci_bar_space_type == PCI::BARSpaceType::IOSpace) {
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#if ARCH(X86_64)
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if (Checked<u64>::addition_would_overflow(pci_bar_value, space_length))
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return Error::from_errno(EOVERFLOW);
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auto io_address_range = TRY(adopt_nonnull_own_or_enomem(new (nothrow) IOAddressData((pci_bar_value & 0xfffffffc), space_length)));
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return TRY(adopt_nonnull_own_or_enomem(new (nothrow) IOWindow(move(io_address_range))));
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#else
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// Note: For non-x86 platforms, IO PCI BARs are simply not useable.
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return Error::from_errno(ENOTSUP);
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#endif
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}
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if (pci_bar_space_type == PCI::BARSpaceType::Memory32BitSpace && Checked<u32>::addition_would_overflow(pci_bar_value, space_length))
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return Error::from_errno(EOVERFLOW);
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if (pci_bar_space_type == PCI::BARSpaceType::Memory16BitSpace && Checked<u16>::addition_would_overflow(pci_bar_value, space_length))
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return Error::from_errno(EOVERFLOW);
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if (pci_bar_space_type == PCI::BARSpaceType::Memory64BitSpace && Checked<u64>::addition_would_overflow(pci_bar_value, space_length))
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return Error::from_errno(EOVERFLOW);
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auto memory_mapped_range = TRY(Memory::adopt_new_nonnull_own_typed_mapping<u8 volatile>(PhysicalAddress(pci_bar_value & PCI::bar_address_mask), space_length, Memory::Region::Access::ReadWrite));
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return TRY(adopt_nonnull_own_or_enomem(new (nothrow) IOWindow(move(memory_mapped_range))));
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}
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ErrorOr<NonnullOwnPtr<IOWindow>> IOWindow::create_for_pci_device_bar(PCI::DeviceIdentifier const& pci_device_identifier, PCI::HeaderType0BaseRegister pci_bar)
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{
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u64 pci_bar_space_size = PCI::get_BAR_space_size(pci_device_identifier, pci_bar);
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return create_for_pci_device_bar(pci_device_identifier, pci_bar, pci_bar_space_size);
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}
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IOWindow::IOWindow(NonnullOwnPtr<Memory::TypedMapping<u8 volatile>> memory_mapped_range)
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: m_space_type(SpaceType::Memory)
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, m_memory_mapped_range(move(memory_mapped_range))
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{
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}
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IOWindow::~IOWindow() = default;
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bool IOWindow::is_access_aligned(u64 offset, size_t byte_size_access) const
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{
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return (offset % byte_size_access) == 0;
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}
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bool IOWindow::is_access_in_range(u64 offset, size_t byte_size_access) const
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{
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if (Checked<u64>::addition_would_overflow(offset, byte_size_access))
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return false;
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#if ARCH(X86_64)
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if (m_space_type == SpaceType::IO) {
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VERIFY(m_io_range);
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VERIFY(!Checked<u64>::addition_would_overflow(m_io_range->address(), m_io_range->space_length()));
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// To understand how we treat IO address space with the corresponding calculation, the Intel Software Developer manual
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// helps us to understand the layout of the IO address space -
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//
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// Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture, 16.3 I/O ADDRESS SPACE, page 16-1 wrote:
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// Any two consecutive 8-bit ports can be treated as a 16-bit port, and any four consecutive ports can be a 32-bit port.
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// In this manner, the processor can transfer 8, 16, or 32 bits to or from a device in the I/O address space.
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// Like words in memory, 16-bit ports should be aligned to even addresses (0, 2, 4, ...) so that all 16 bits can be transferred in a single bus cycle.
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// Likewise, 32-bit ports should be aligned to addresses that are multiples of four (0, 4, 8, ...).
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// The processor supports data transfers to unaligned ports, but there is a performance penalty because one or more
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// extra bus cycle must be used.
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return (m_io_range->address() + m_io_range->space_length()) >= (offset + byte_size_access);
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}
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#endif
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VERIFY(space_type() == SpaceType::Memory);
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VERIFY(m_memory_mapped_range);
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VERIFY(!Checked<u64>::addition_would_overflow(m_memory_mapped_range->offset, m_memory_mapped_range->length));
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return (m_memory_mapped_range->offset + m_memory_mapped_range->length) >= (offset + byte_size_access);
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}
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u8 IOWindow::read8(u64 offset)
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{
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VERIFY(is_access_in_range(offset, sizeof(u8)));
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u8 data { 0 };
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in<u8>(offset, data);
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return data;
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}
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u16 IOWindow::read16(u64 offset)
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{
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// Note: Although it might be OK to allow unaligned access on regular memory,
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// for memory mapped IO access, it should always be considered a bug.
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// The same goes for port mapped IO access, because in x86 unaligned access to ports
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// is possible but there's a performance penalty.
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VERIFY(is_access_in_range(offset, sizeof(u16)));
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VERIFY(is_access_aligned(offset, sizeof(u16)));
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u16 data { 0 };
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in<u16>(offset, data);
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return data;
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}
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u32 IOWindow::read32(u64 offset)
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{
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// Note: Although it might be OK to allow unaligned access on regular memory,
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// for memory mapped IO access, it should always be considered a bug.
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// The same goes for port mapped IO access, because in x86 unaligned access to ports
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// is possible but there's a performance penalty.
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VERIFY(is_access_in_range(offset, sizeof(u32)));
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VERIFY(is_access_aligned(offset, sizeof(u32)));
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u32 data { 0 };
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in<u32>(offset, data);
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return data;
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}
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void IOWindow::write8(u64 offset, u8 data)
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{
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VERIFY(is_access_in_range(offset, sizeof(u8)));
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out<u8>(offset, data);
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}
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void IOWindow::write16(u64 offset, u16 data)
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{
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// Note: Although it might be OK to allow unaligned access on regular memory,
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// for memory mapped IO access, it should always be considered a bug.
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// The same goes for port mapped IO access, because in x86 unaligned access to ports
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// is possible but there's a performance penalty.
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VERIFY(is_access_in_range(offset, sizeof(u16)));
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VERIFY(is_access_aligned(offset, sizeof(u16)));
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out<u16>(offset, data);
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}
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void IOWindow::write32(u64 offset, u32 data)
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{
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// Note: Although it might be OK to allow unaligned access on regular memory,
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// for memory mapped IO access, it should always be considered a bug.
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// The same goes for port mapped IO access, because in x86 unaligned access to ports
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// is possible but there's a performance penalty.
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VERIFY(is_access_in_range(offset, sizeof(u32)));
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VERIFY(is_access_aligned(offset, sizeof(u32)));
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out<u32>(offset, data);
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}
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void IOWindow::write32_unaligned(u64 offset, u32 data)
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{
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// Note: We only verify that we access IO in the expected range.
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// Note: for port mapped IO access, because in x86 unaligned access to ports
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// is possible but there's a performance penalty, we can still allow that to happen.
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// However, it should be noted that most cases should not use unaligned access
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// to hardware IO, so this is a valid case in emulators or hypervisors only.
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// Note: Using this for memory mapped IO will fail for unaligned access, because
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// there's no valid use case for it (yet).
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VERIFY(space_type() != SpaceType::Memory);
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VERIFY(is_access_in_range(offset, sizeof(u32)));
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out<u32>(offset, data);
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}
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u32 IOWindow::read32_unaligned(u64 offset)
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{
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// Note: We only verify that we access IO in the expected range.
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// Note: for port mapped IO access, because in x86 unaligned access to ports
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// is possible but there's a performance penalty, we can still allow that to happen.
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// However, it should be noted that most cases should not use unaligned access
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// to hardware IO, so this is a valid case in emulators or hypervisors only.
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// Note: Using this for memory mapped IO will fail for unaligned access, because
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// there's no valid use case for it (yet).
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VERIFY(space_type() != SpaceType::Memory);
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VERIFY(is_access_in_range(offset, sizeof(u32)));
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u32 data { 0 };
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in<u32>(offset, data);
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return data;
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}
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PhysicalAddress IOWindow::as_physical_memory_address() const
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{
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VERIFY(space_type() == SpaceType::Memory);
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VERIFY(m_memory_mapped_range);
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return m_memory_mapped_range->paddr;
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}
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u8 volatile* IOWindow::as_memory_address_pointer()
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{
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VERIFY(space_type() == SpaceType::Memory);
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VERIFY(m_memory_mapped_range);
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return m_memory_mapped_range->ptr();
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}
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#if ARCH(X86_64)
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IOAddress IOWindow::as_io_address() const
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{
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VERIFY(space_type() == SpaceType::IO);
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VERIFY(m_io_range);
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return IOAddress(m_io_range->address());
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}
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#endif
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}
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