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https://github.com/RGBCube/serenity
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9ee098b119
Like the HID, Audio and Storage subsystem, the Graphics subsystem (which
handles GPUs technically) exposes unix device files (typically in /dev).
To ensure consistency across the repository, move all related files to a
new directory under Kernel/Devices called "GPU".
Also remove the redundant "GPU" word from the VirtIO driver directory,
and the word "Graphics" from GraphicsManagement.{h,cpp} filenames.
89 lines
5 KiB
C++
89 lines
5 KiB
C++
/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Devices/GPU/Intel/Transcoder/AnalogDisplayTranscoder.h>
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#include <Kernel/Memory/PhysicalAddress.h>
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namespace Kernel {
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ErrorOr<NonnullOwnPtr<IntelAnalogDisplayTranscoder>> IntelAnalogDisplayTranscoder::create_with_physical_addresses(PhysicalAddress transcoder_registers_start_address,
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PhysicalAddress pipe_registers_start_address, PhysicalAddress dpll_registers_start_address, PhysicalAddress dpll_multiplier_register_start_address)
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{
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auto transcoder_registers_mapping = TRY(Memory::map_typed<TranscoderRegisters volatile>(transcoder_registers_start_address, sizeof(IntelDisplayTranscoder::TranscoderRegisters), Memory::Region::Access::ReadWrite));
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auto pipe_registers_mapping = TRY(Memory::map_typed<PipeRegisters volatile>(pipe_registers_start_address, sizeof(IntelDisplayTranscoder::PipeRegisters), Memory::Region::Access::ReadWrite));
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auto dpll_registers_mapping = TRY(Memory::map_typed<DPLLRegisters volatile>(dpll_registers_start_address, sizeof(DPLLRegisters), Memory::Region::Access::ReadWrite));
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auto dpll_control_mapping = TRY(Memory::map_typed<DPLLControlRegisters volatile>(dpll_multiplier_register_start_address, sizeof(DPLLControlRegisters), Memory::Region::Access::ReadWrite));
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return adopt_nonnull_own_or_enomem(new (nothrow) IntelAnalogDisplayTranscoder(move(transcoder_registers_mapping), move(pipe_registers_mapping), move(dpll_registers_mapping), move(dpll_control_mapping)));
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}
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IntelAnalogDisplayTranscoder::IntelAnalogDisplayTranscoder(Memory::TypedMapping<TranscoderRegisters volatile> transcoder_registers_mapping,
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Memory::TypedMapping<PipeRegisters volatile> pipe_registers_mapping, Memory::TypedMapping<DPLLRegisters volatile> dpll_registers_mapping, Memory::TypedMapping<DPLLControlRegisters volatile> dpll_control_registers)
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: IntelDisplayTranscoder(move(transcoder_registers_mapping), move(pipe_registers_mapping))
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, m_dpll_registers(move(dpll_registers_mapping))
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, m_dpll_control_registers(move(dpll_control_registers))
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{
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}
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ErrorOr<void> IntelAnalogDisplayTranscoder::set_dpll_settings(Badge<IntelDisplayConnectorGroup>, IntelGraphics::PLLSettings const& settings, size_t dac_multiplier)
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{
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SpinlockLocker locker(m_access_lock);
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u32 value = (settings.m2 - 2) | ((settings.m1 - 2) << 8) | ((settings.n - 2) << 16);
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m_dpll_registers->divisor_a0 = value;
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m_dpll_registers->divisor_a1 = value;
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m_shadow_registers.dpll_divisor_a0 = value;
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m_shadow_registers.dpll_divisor_a1 = value;
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// Note: We don't set the DAC multiplier now but reserve it for later usage (e.g. when enabling the DPLL)
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m_shadow_registers.dpll_reserved_dac_multiplier = dac_multiplier;
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// Note: We don't set the DPLL P1 now but reserve it for later usage (e.g. when enabling the DPLL)
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m_shadow_registers.dpll_p1 = settings.p1;
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return {};
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}
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ErrorOr<void> IntelAnalogDisplayTranscoder::enable_dpll_without_vga(Badge<IntelDisplayConnectorGroup>)
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{
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SpinlockLocker locker(m_access_lock);
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// Explanation for Gen4 DPLL control bits:
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// 1. 0b0110 in bits 9 to 12 - use clock phase 6 (Default)
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// 2. bits 24,25 - set to 0b00 to ensure FPA0/FPA1 (DPLL A Divisor 0, 1) divide by 10 (used for DAC modes under 270 MHz)
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// 3. bit 26 - set to 0b1 to ensure mode select to DAC mode
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// 4. bit 28 - set to 0b1 to disable VGA mode
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// 5. bit 31 - enable DPLL VCO (DPLL enabled and operational)
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u32 control_value = (6 << 9) | (m_shadow_registers.dpll_p1) << 16 | (1 << 26) | (1 << 28) | (1 << 31);
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m_dpll_control_registers->control = control_value;
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m_shadow_registers.dpll_control = control_value;
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// Explanation for Gen4 DPLL multiplier bits:
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// 1. 0b0110 in bits 9 to 12 - use clock phase 6 (Default)
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// 2. bits 24,25 - set to 0b00 to ensure FPA0/FPA1 (DPLL A Divisor 0, 1) divide by 10 (used for DAC modes under 270 MHz)
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// 3. bit 26 - set to 0b1 to ensure mode select to DAC mode
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// 4. bit 28 - set to 0b1 to disable VGA mode
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// 5. bit 31 - enable DPLL VCO (DPLL enabled and operational)
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u32 dac_multiplier_value = (m_shadow_registers.dpll_reserved_dac_multiplier - 1) | ((m_shadow_registers.dpll_reserved_dac_multiplier - 1) << 8);
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m_dpll_control_registers->multiplier = dac_multiplier_value;
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m_shadow_registers.dpll_raw_dac_multiplier = dac_multiplier_value;
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// The specification says we should wait (at least) about 150 microseconds
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// after enabling the DPLL to allow the clock to stabilize
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microseconds_delay(200);
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for (size_t milliseconds_elapsed = 0; milliseconds_elapsed < 5; milliseconds_elapsed++) {
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u32 control_value = m_dpll_control_registers->control;
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if (control_value & (1 << 31))
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return {};
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}
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return Error::from_errno(EBUSY);
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}
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ErrorOr<void> IntelAnalogDisplayTranscoder::disable_dpll(Badge<IntelDisplayConnectorGroup>)
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{
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SpinlockLocker locker(m_access_lock);
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m_dpll_control_registers->control = 0;
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m_shadow_registers.dpll_control = 0;
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return {};
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}
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}
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