mirror of
https://github.com/RGBCube/serenity
synced 2025-05-31 15:28:11 +00:00
7138395982
Shadow doorbell feature was added in the NVMe spec to improve the performance of virtual devices. Typically, ringing a doorbell involves writing to an MMIO register in QEMU, which can be expensive as there will be a trap for the VM. Shadow doorbell mechanism was added for the VM to communicate with the OS when it needs to do an MMIO write, thereby avoiding it when it is not necessary. There is no performance improvement with this support in Serenity at the moment because of the block layer constraint of not batching multiple IOs. Once the command batching support is added to the block layer, shadow doorbell support can improve performance by avoiding many MMIO writes. Default to old MMIO mechanism if shadow doorbell is not supported.
87 lines
2.9 KiB
C++
87 lines
2.9 KiB
C++
/*
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* Copyright (c) 2021, Pankaj R <pankydev8@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/OwnPtr.h>
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#include <AK/Time.h>
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#include <AK/Tuple.h>
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#include <AK/Types.h>
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#include <Kernel/Bus/PCI/Device.h>
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#include <Kernel/Devices/Storage/NVMe/NVMeDefinitions.h>
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#include <Kernel/Devices/Storage/NVMe/NVMeNameSpace.h>
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#include <Kernel/Devices/Storage/NVMe/NVMeQueue.h>
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#include <Kernel/Devices/Storage/StorageController.h>
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#include <Kernel/Library/LockRefPtr.h>
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#include <Kernel/Library/NonnullLockRefPtr.h>
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#include <Kernel/Locking/Spinlock.h>
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#include <Kernel/Memory/TypedMapping.h>
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namespace Kernel {
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class NVMeController : public PCI::Device
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, public StorageController {
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public:
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static ErrorOr<NonnullRefPtr<NVMeController>> try_initialize(PCI::DeviceIdentifier const&, bool is_queue_polled);
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ErrorOr<void> initialize(bool is_queue_polled);
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LockRefPtr<StorageDevice> device(u32 index) const override;
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size_t devices_count() const override;
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virtual StringView device_name() const override { return "NVMeController"sv; }
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protected:
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ErrorOr<void> reset() override;
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ErrorOr<void> shutdown() override;
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void complete_current_request(AsyncDeviceRequest::RequestResult result) override;
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public:
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ErrorOr<void> reset_controller();
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ErrorOr<void> start_controller();
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u32 get_admin_q_dept();
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u16 submit_admin_command(NVMeSubmission& sub, bool sync = false)
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{
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// First queue is always the admin queue
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if (sync) {
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return m_admin_queue->submit_sync_sqe(sub);
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}
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m_admin_queue->submit_sqe(sub);
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return 0;
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}
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bool is_admin_queue_ready() { return m_admin_queue_ready; }
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void set_admin_queue_ready_flag() { m_admin_queue_ready = true; }
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private:
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NVMeController(PCI::DeviceIdentifier const&, u32 hardware_relative_controller_id);
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ErrorOr<void> identify_and_init_namespaces();
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ErrorOr<void> identify_and_init_controller();
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Tuple<u64, u8> get_ns_features(IdentifyNamespace& identify_data_struct);
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ErrorOr<void> create_admin_queue(QueueType queue_type);
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ErrorOr<void> create_io_queue(u8 qid, QueueType queue_type);
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void calculate_doorbell_stride()
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{
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m_dbl_stride = (m_controller_regs->cap >> CAP_DBL_SHIFT) & CAP_DBL_MASK;
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}
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bool wait_for_ready(bool);
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private:
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LockRefPtr<NVMeQueue> m_admin_queue;
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Vector<NonnullLockRefPtr<NVMeQueue>> m_queues;
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Vector<NonnullLockRefPtr<NVMeNameSpace>> m_namespaces;
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Memory::TypedMapping<ControllerRegister volatile> m_controller_regs;
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RefPtr<Memory::PhysicalPage> m_dbbuf_shadow_page;
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RefPtr<Memory::PhysicalPage> m_dbbuf_eventidx_page;
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bool m_admin_queue_ready { false };
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size_t m_device_count { 0 };
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AK::Duration m_ready_timeout;
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u32 m_bar { 0 };
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u8 m_dbl_stride { 0 };
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PCI::InterruptType m_irq_type;
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QueueType m_queue_type { QueueType::IRQ };
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static Atomic<u8> s_controller_id;
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};
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}
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