mirror of
https://github.com/RGBCube/serenity
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7c0540a229
This has KString, KBuffer, DoubleBuffer, KBufferBuilder, IOWindow, UserOrKernelBuffer and ScopedCritical classes being moved to the Kernel/Library subdirectory. Also, move the panic and assertions handling code to that directory.
104 lines
3.5 KiB
C++
104 lines
3.5 KiB
C++
/*
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* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/Interrupts.h>
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#include <Kernel/Arch/x86_64/IO.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Bus/PCI/Access.h>
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#include <Kernel/Bus/PCI/Initializer.h>
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#include <Kernel/CommandLine.h>
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#include <Kernel/FileSystem/SysFS/Subsystems/Bus/PCI/BusDirectory.h>
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#include <Kernel/Firmware/ACPI/Parser.h>
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#include <Kernel/Library/Panic.h>
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#include <Kernel/Sections.h>
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namespace Kernel::PCI {
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READONLY_AFTER_INIT bool g_pci_access_io_probe_failed;
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READONLY_AFTER_INIT bool g_pci_access_is_disabled_from_commandline;
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static bool test_pci_io();
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UNMAP_AFTER_INIT static PCIAccessLevel detect_optimal_access_type()
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{
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auto boot_determined = kernel_command_line().pci_access_level();
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if (!ACPI::is_enabled() || !ACPI::Parser::the()->find_table("MCFG"sv).has_value())
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return PCIAccessLevel::IOAddressing;
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if (boot_determined != PCIAccessLevel::IOAddressing)
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return boot_determined;
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if (!g_pci_access_io_probe_failed)
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return PCIAccessLevel::IOAddressing;
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PANIC("No PCI bus access method detected!");
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}
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UNMAP_AFTER_INIT void initialize()
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{
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g_pci_access_is_disabled_from_commandline = kernel_command_line().is_pci_disabled();
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Optional<PhysicalAddress> possible_mcfg;
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// FIXME: There are other arch-specific methods to find the memory range
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// for accessing the PCI configuration space.
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// For example, the QEMU microvm machine type might expose an FDT so we could
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// parse it to find a PCI host bridge.
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if (ACPI::is_enabled()) {
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possible_mcfg = ACPI::Parser::the()->find_table("MCFG"sv);
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g_pci_access_io_probe_failed = (!test_pci_io()) && (!possible_mcfg.has_value());
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} else {
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g_pci_access_io_probe_failed = !test_pci_io();
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}
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if (g_pci_access_is_disabled_from_commandline || g_pci_access_io_probe_failed)
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return;
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switch (detect_optimal_access_type()) {
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case PCIAccessLevel::MemoryAddressing: {
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VERIFY(possible_mcfg.has_value());
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auto success = Access::initialize_for_multiple_pci_domains(possible_mcfg.value());
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VERIFY(success);
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break;
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}
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case PCIAccessLevel::IOAddressing: {
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auto success = Access::initialize_for_one_pci_domain();
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VERIFY(success);
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break;
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}
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default:
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VERIFY_NOT_REACHED();
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}
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PCIBusSysFSDirectory::initialize();
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// IRQ from pin-based interrupt should be set as reserved as soon as possible so that the PCI device
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// that chooses to use MSI(x) based interrupt can avoid sharing the IRQ with other devices.
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MUST(PCI::enumerate([&](DeviceIdentifier const& device_identifier) {
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// A simple sanity check to avoid getting a panic in get_interrupt_handler() before setting the IRQ as reserved.
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if (auto irq = device_identifier.interrupt_line().value(); irq < GENERIC_INTERRUPT_HANDLERS_COUNT) {
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auto& handler = get_interrupt_handler(irq);
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handler.set_reserved();
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}
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}));
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MUST(PCI::enumerate([&](DeviceIdentifier const& device_identifier) {
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dmesgln("{} {}", device_identifier.address(), device_identifier.hardware_id());
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}));
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}
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UNMAP_AFTER_INIT bool test_pci_io()
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{
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dmesgln("Testing PCI via manual probing...");
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u32 tmp = 0x80000000;
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IO::out32(PCI::address_port, tmp);
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tmp = IO::in32(PCI::address_port);
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if (tmp == 0x80000000) {
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dmesgln("PCI IO supported");
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return true;
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}
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dmesgln("PCI IO not supported");
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return false;
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}
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}
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