mirror of
https://github.com/RGBCube/serenity
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4409b33145
This makes it possible to use MakeIndexSequqnce in functions like:
template<typename T, size_t N>
constexpr auto foo(T (&a)[N])
This means AK/StdLibExtraDetails.h must now include AK/Types.h
for size_t, which means AK/Types.h can no longer include
AK/StdLibExtras.h (which arguably it shouldn't do anyways),
which requires rejiggering some things.
(IMHO Types.h shouldn't use AK::Details metaprogramming at all.
FlatPtr doesn't necessarily have to use Conditional<> and ssize_t could
maybe be in its own header or something. But since it's tangential to
this PR, going with the tried and true "lift things that cause the
cycle up to the top" approach.)
387 lines
12 KiB
C++
387 lines
12 KiB
C++
/*
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* Copyright (c) 2023, Sönke Holz <sholz8530@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/BitCast.h>
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#include <AK/Format.h>
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#include <AK/StdLibExtras.h>
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#include <AK/Types.h>
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#include <AK/Platform.h>
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VALIDATE_IS_RISCV64()
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// Documentation for the CSRs:
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// RISC-V ISA Manual, Volume II (https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf)
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namespace Kernel::RISCV64::CSR {
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// 2.2 CSR Listing
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enum class Address : u16 {
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// Supervisor Trap Setup
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SSTATUS = 0x100,
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SIE = 0x104,
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STVEC = 0x105,
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// Supervisor Protection and Translation
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SATP = 0x180,
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// Unprivileged Counters/Timers
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TIME = 0xc01,
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};
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ALWAYS_INLINE FlatPtr read(Address address)
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{
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FlatPtr ret;
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asm volatile("csrr %0, %1"
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: "=r"(ret)
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: "i"(address));
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return ret;
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}
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ALWAYS_INLINE void write(Address address, FlatPtr value)
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{
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asm volatile("csrw %0, %1" ::"i"(address), "Kr"(value));
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}
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ALWAYS_INLINE FlatPtr read_and_set_bits(Address address, FlatPtr bit_mask)
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{
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FlatPtr ret;
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asm volatile("csrrs %0, %1, %2"
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: "=r"(ret)
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: "i"(address), "Kr"(bit_mask));
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return ret;
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}
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ALWAYS_INLINE void set_bits(Address address, FlatPtr bit_mask)
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{
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asm volatile("csrs %0, %1" ::"i"(address), "Kr"(bit_mask));
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}
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ALWAYS_INLINE void clear_bits(Address address, FlatPtr bit_mask)
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{
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asm volatile("csrc %0, %1" ::"i"(address), "Kr"(bit_mask));
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}
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// 4.1.11 Supervisor Address Translation and Protection (satp) Register
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struct [[gnu::packed]] alignas(u64) SATP {
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enum class Mode : u64 {
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Bare = 0,
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Sv39 = 8,
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Sv48 = 9,
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Sv67 = 10,
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};
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// Physical page number of root page table
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u64 PPN : 44;
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// Address space identifier
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u64 ASID : 16;
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// Current address-translation scheme
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Mode MODE : 4;
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static ALWAYS_INLINE void write(SATP satp)
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{
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CSR::write(CSR::Address::SATP, bit_cast<FlatPtr>(satp));
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}
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static ALWAYS_INLINE SATP read()
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{
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return bit_cast<SATP>(CSR::read(CSR::Address::SATP));
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}
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};
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static_assert(AssertSize<SATP, 8>());
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// 4.1.1 Supervisor Status Register (sstatus)
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struct [[gnu::packed]] alignas(u64) SSTATUS {
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// Useful for CSR::{set,clear}_bits
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enum class Offset {
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SIE = 1,
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SPIE = 5,
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UBE = 6,
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SPP = 8,
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VS = 9,
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FS = 13,
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XS = 15,
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SUM = 18,
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MXR = 19,
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UXL = 32,
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SD = 63,
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};
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enum class PrivilegeMode : u64 {
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User = 0,
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Supervisor = 1,
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};
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enum class FloatingPointStatus : u64 {
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Off = 0,
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Initial = 1,
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Clean = 2,
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Dirty = 3,
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};
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enum class VectorStatus : u64 {
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Off = 0,
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Initial = 1,
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Clean = 2,
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Dirty = 3,
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};
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enum class UserModeExtensionsStatus : u64 {
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AllOff = 0,
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NoneDirtyOrClean_SomeOn = 1,
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NoneDirty_SomeOn = 2,
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SomeDirty = 3,
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};
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enum class XLEN : u64 {
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Bits32 = 1,
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Bits64 = 2,
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Bits128 = 3,
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};
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u64 _reserved0 : 1;
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// Enables or disables all interrupts in supervisor mode
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u64 SIE : 1;
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u64 _reserved2 : 3;
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// Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode
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// When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0. When
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// an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.
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u64 SPIE : 1;
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// Controls the endianness of explicit memory accesses made from
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// U-mode, which may differ from the endianness of memory accesses in S-mode
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u64 UBE : 1;
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u64 _reserved7 : 1;
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// Indicates the privilege level at which a hart was executing before entering supervisor mode
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PrivilegeMode SPP : 1;
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// Encodes the status of the vector extension state, including the vector registers v0–v31 and
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// the CSRs vcsr, vxrm, vxsat, vstart, vl, vtype, and vlenb.
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VectorStatus VS : 2;
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u64 _reserved11 : 2;
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// Encodes the status of the floating-point unit state,
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// including the floating-point registers f0–f31 and the CSRs fcsr, frm, and fflags.
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FloatingPointStatus FS : 2;
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// The XS field encodes the status of additional user-mode extensions and associated state.
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UserModeExtensionsStatus XS : 2;
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u64 _reserved17 : 1;
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// The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode
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// loads and stores access virtual memory. When SUM=0, S-mode memory accesses to pages that are
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// accessible by U-mode (U=1 in Figure 5.18) will fault. When SUM=1, these accesses are permitted.
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// SUM has no effect when page-based virtual memory is not in effect, nor when executing in U-mode.
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// Note that S-mode can never execute instructions from user pages, regardless of the state of SUM.
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u64 SUM : 1;
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// The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual
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// memory. When MXR=0, only loads from pages marked readable (R=1 in Figure 5.18) will succeed.
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// When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed.
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// MXR has no effect when page-based virtual memory is not in effect.
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u64 MXR : 1;
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u64 _reserved20 : 12;
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// Controls the value of XLEN for U-mode
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XLEN UXL : 2;
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u64 _reserved34 : 29;
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// The SD bit is a read-only bit that summarizes whether either the FS, VS, or XS fields signal the
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// presence of some dirty state that will require saving extended user context to memory.
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u64 SD : 1;
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static ALWAYS_INLINE void write(SSTATUS sstatus)
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{
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CSR::write(CSR::Address::SSTATUS, bit_cast<FlatPtr>(sstatus));
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}
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static ALWAYS_INLINE SSTATUS read()
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{
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return bit_cast<SSTATUS>(CSR::read(CSR::Address::SSTATUS));
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}
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};
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static_assert(AssertSize<SSTATUS, 8>());
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// 4.1.8 Supervisor Cause Register (scause)
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constexpr u64 SCAUSE_INTERRUPT_MASK = 1LU << 63;
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enum class SCAUSE : u64 {
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// Interrupts
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SupervisorSoftwareInterrupt = SCAUSE_INTERRUPT_MASK | 1,
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SupervisorTimerInterrupt = SCAUSE_INTERRUPT_MASK | 5,
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SupervisorExternalInterrupt = SCAUSE_INTERRUPT_MASK | 9,
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// Exceptions
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InstructionAddressMisaligned = 0,
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InstructionAccessFault = 1,
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IllegalInstrction = 2,
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Breakpoint = 3,
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LoadAddressMisaligned = 4,
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LoadAccessFault = 5,
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StoreOrAMOAddressMisaligned = 6,
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StoreOrAMOAccessFault = 7,
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EnvironmentCallFromUMode = 8,
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EnvironmentCallFromSMode = 9,
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InstructionPageFault = 12,
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LoadPageFault = 13,
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StoreOrAMOPageFault = 15,
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};
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}
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template<>
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struct AK::Formatter<Kernel::RISCV64::CSR::SSTATUS> : AK::Formatter<FormatString> {
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ErrorOr<void> format(FormatBuilder& builder, Kernel::RISCV64::CSR::SSTATUS value)
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{
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if (value.SD)
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TRY(builder.put_literal("SD "sv));
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switch (value.UXL) {
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case Kernel::RISCV64::CSR::SSTATUS::XLEN::Bits32:
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TRY(builder.put_literal("UXL=32 "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::XLEN::Bits64:
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TRY(builder.put_literal("UXL=64 "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::XLEN::Bits128:
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TRY(builder.put_literal("UXL=128 "sv));
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break;
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}
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if (value.MXR)
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TRY(builder.put_literal("MXR "sv));
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if (value.SUM)
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TRY(builder.put_literal("SUM "sv));
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switch (value.XS) {
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case Kernel::RISCV64::CSR::SSTATUS::UserModeExtensionsStatus::AllOff:
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TRY(builder.put_literal("XS=AllOff "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::UserModeExtensionsStatus::NoneDirtyOrClean_SomeOn:
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TRY(builder.put_literal("XS=NoneDirtyOrClean_SomeOn "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::UserModeExtensionsStatus::NoneDirty_SomeOn:
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TRY(builder.put_literal("XS=NoneDirty_SomeOn "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::UserModeExtensionsStatus::SomeDirty:
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TRY(builder.put_literal("XS=SomeDirty "sv));
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break;
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}
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switch (value.FS) {
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case Kernel::RISCV64::CSR::SSTATUS::FloatingPointStatus::Off:
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TRY(builder.put_literal("FS=Off "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::FloatingPointStatus::Initial:
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TRY(builder.put_literal("FS=Initial "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::FloatingPointStatus::Clean:
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TRY(builder.put_literal("FS=Clean "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::FloatingPointStatus::Dirty:
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TRY(builder.put_literal("FS=Dirty "sv));
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break;
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}
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switch (value.VS) {
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case Kernel::RISCV64::CSR::SSTATUS::VectorStatus::Off:
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TRY(builder.put_literal("VS=Off "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::VectorStatus::Initial:
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TRY(builder.put_literal("VS=Initial "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::VectorStatus::Clean:
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TRY(builder.put_literal("VS=Clean "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::VectorStatus::Dirty:
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TRY(builder.put_literal("VS=Dirty "sv));
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break;
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}
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switch (value.SPP) {
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case Kernel::RISCV64::CSR::SSTATUS::PrivilegeMode::User:
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TRY(builder.put_literal("SPP=User "sv));
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break;
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case Kernel::RISCV64::CSR::SSTATUS::PrivilegeMode::Supervisor:
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TRY(builder.put_literal("SPP=Supervisor "sv));
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break;
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}
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if (value.UBE)
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TRY(builder.put_literal("UBE "sv));
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if (value.SPIE)
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TRY(builder.put_literal("SPIE "sv));
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if (value.SIE)
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TRY(builder.put_literal("SIE "sv));
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TRY(builder.put_literal("("sv));
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TRY(builder.put_u64(bit_cast<u64>(value), 16, true, false, true, false, FormatBuilder::Align::Right, 16));
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TRY(builder.put_literal(")"sv));
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return {};
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}
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};
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template<>
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struct AK::Formatter<Kernel::RISCV64::CSR::SCAUSE> : AK::Formatter<FormatString> {
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ErrorOr<void> format(FormatBuilder& builder, Kernel::RISCV64::CSR::SCAUSE value)
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{
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switch (value) {
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case Kernel::RISCV64::CSR::SCAUSE::SupervisorSoftwareInterrupt:
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return builder.put_string("Supervisor software interrupt"sv);
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case Kernel::RISCV64::CSR::SCAUSE::SupervisorTimerInterrupt:
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return builder.put_string("Supervisor timer interrupt"sv);
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case Kernel::RISCV64::CSR::SCAUSE::SupervisorExternalInterrupt:
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return builder.put_string("Supervisor external interrupt"sv);
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case Kernel::RISCV64::CSR::SCAUSE::InstructionAddressMisaligned:
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return builder.put_string("Instruction address misaligned"sv);
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case Kernel::RISCV64::CSR::SCAUSE::InstructionAccessFault:
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return builder.put_string("Instruction access fault"sv);
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case Kernel::RISCV64::CSR::SCAUSE::IllegalInstrction:
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return builder.put_string("Illegal instruction"sv);
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case Kernel::RISCV64::CSR::SCAUSE::Breakpoint:
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return builder.put_string("Breakpoint"sv);
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case Kernel::RISCV64::CSR::SCAUSE::LoadAddressMisaligned:
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return builder.put_string("Load address misaligned"sv);
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case Kernel::RISCV64::CSR::SCAUSE::LoadAccessFault:
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return builder.put_string("Load access fault"sv);
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case Kernel::RISCV64::CSR::SCAUSE::StoreOrAMOAddressMisaligned:
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return builder.put_string("Store/AMO address misaligned"sv);
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case Kernel::RISCV64::CSR::SCAUSE::StoreOrAMOAccessFault:
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return builder.put_string("Store/AMO access fault"sv);
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case Kernel::RISCV64::CSR::SCAUSE::EnvironmentCallFromUMode:
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return builder.put_string("Environment call from U-mode"sv);
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case Kernel::RISCV64::CSR::SCAUSE::EnvironmentCallFromSMode:
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return builder.put_string("Environment call from S-mode"sv);
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case Kernel::RISCV64::CSR::SCAUSE::InstructionPageFault:
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return builder.put_string("Instruction page fault"sv);
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case Kernel::RISCV64::CSR::SCAUSE::LoadPageFault:
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return builder.put_string("Load page fault"sv);
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case Kernel::RISCV64::CSR::SCAUSE::StoreOrAMOPageFault:
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return builder.put_string("Store/AMO page fault"sv);
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default:
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VERIFY_NOT_REACHED();
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}
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}
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};
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