mirror of
https://github.com/RGBCube/serenity
synced 2025-05-22 14:15:08 +00:00
05ba034000
This class is intended to replace all IOAddress usages in the Kernel
codebase altogether. The idea is to ensure IO can be done in
arch-specific manner that is determined mostly in compile-time, but to
still be able to use most of the Kernel code in non-x86 builds. Specific
devices that rely on x86-specific IO instructions are already placed in
the Arch/x86 directory and are omitted for non-x86 builds.
The reason this works so well is the fact that x86 IO space acts in a
similar fashion to the traditional memory space being available in most
CPU architectures - the x86 IO space is essentially just an array of
bytes like the physical memory address space, but requires x86 IO
instructions to load and store data. Therefore, many devices allow host
software to interact with the hardware registers in both ways, with a
noticeable trend even in the modern x86 hardware to move away from the
old x86 IO space to exclusively using memory-mapped IO.
Therefore, the IOWindow class encapsulates both methods for x86 builds.
The idea is to allow PCI devices to be used in either way in x86 builds,
so when trying to map an IOWindow on a PCI BAR, the Kernel will try to
find the proper method being declared with the PCI BAR flags.
For old PCI hardware on non-x86 builds this might turn into a problem as
we can't use port mapped IO, so the Kernel will gracefully fail with
ENOTSUP error code if that's the case, as there's really nothing we can
do within such case.
For general IO, the read{8,16,32} and write{8,16,32} methods are
available as a convenient API for other places in the Kernel. There are
simply no direct 64-bit IO API methods yet, as it's not needed right now
and is not considered to be Arch-agnostic too - the x86 IO space doesn't
support generating 64 bit cycle on IO bus and instead requires two 2
32-bit accesses. If for whatever reason it appears to be necessary to do
IO in such manner, it could probably be added with some neat tricks to
do so. It is recommended to use Memory::TypedMapping struct if direct 64
bit IO is actually needed.
122 lines
5 KiB
C++
122 lines
5 KiB
C++
/*
|
|
* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
|
|
* Copyright (c) 2020-2021, Jesse Buhagiar <jooster669@gmail.com>
|
|
*
|
|
* SPDX-License-Identifier: BSD-2-Clause
|
|
*/
|
|
|
|
#pragma once
|
|
|
|
#include <AK/Array.h>
|
|
#include <AK/NonnullOwnPtr.h>
|
|
#include <AK/Platform.h>
|
|
#include <Kernel/Bus/PCI/Device.h>
|
|
#include <Kernel/Bus/USB/UHCI/UHCIDescriptorPool.h>
|
|
#include <Kernel/Bus/USB/UHCI/UHCIDescriptorTypes.h>
|
|
#include <Kernel/Bus/USB/UHCI/UHCIRootHub.h>
|
|
#include <Kernel/Bus/USB/USBController.h>
|
|
#include <Kernel/IOWindow.h>
|
|
#include <Kernel/Interrupts/IRQHandler.h>
|
|
#include <Kernel/Locking/Spinlock.h>
|
|
#include <Kernel/Memory/AnonymousVMObject.h>
|
|
#include <Kernel/Process.h>
|
|
#include <Kernel/Time/TimeManagement.h>
|
|
|
|
namespace Kernel::USB {
|
|
|
|
class UHCIController final
|
|
: public USBController
|
|
, public PCI::Device
|
|
, public IRQHandler {
|
|
|
|
static constexpr u8 MAXIMUM_NUMBER_OF_TDS = 128; // Upper pool limit. This consumes the second page we have allocated
|
|
static constexpr u8 MAXIMUM_NUMBER_OF_QHS = 64;
|
|
static constexpr u8 NUMBER_OF_INTERRUPT_QHS = 11;
|
|
|
|
public:
|
|
static constexpr u8 NUMBER_OF_ROOT_PORTS = 2;
|
|
static ErrorOr<NonnullLockRefPtr<UHCIController>> try_to_initialize(PCI::DeviceIdentifier const& pci_device_identifier);
|
|
virtual ~UHCIController() override;
|
|
|
|
virtual StringView purpose() const override { return "UHCI"sv; }
|
|
|
|
virtual ErrorOr<void> initialize() override;
|
|
virtual ErrorOr<void> reset() override;
|
|
virtual ErrorOr<void> stop() override;
|
|
virtual ErrorOr<void> start() override;
|
|
ErrorOr<void> spawn_port_process();
|
|
|
|
virtual ErrorOr<size_t> submit_control_transfer(Transfer& transfer) override;
|
|
virtual ErrorOr<size_t> submit_bulk_transfer(Transfer& transfer) override;
|
|
|
|
void get_port_status(Badge<UHCIRootHub>, u8, HubStatus&);
|
|
ErrorOr<void> set_port_feature(Badge<UHCIRootHub>, u8, HubFeatureSelector);
|
|
ErrorOr<void> clear_port_feature(Badge<UHCIRootHub>, u8, HubFeatureSelector);
|
|
|
|
private:
|
|
UHCIController(PCI::DeviceIdentifier const& pci_device_identifier, NonnullOwnPtr<IOWindow> registers_io_window);
|
|
|
|
u16 read_usbcmd() { return m_registers_io_window->read16(0); }
|
|
u16 read_usbsts() { return m_registers_io_window->read16(0x2); }
|
|
u16 read_usbintr() { return m_registers_io_window->read16(0x4); }
|
|
u16 read_frnum() { return m_registers_io_window->read16(0x6); }
|
|
u32 read_flbaseadd() { return m_registers_io_window->read32(0x8); }
|
|
u8 read_sofmod() { return m_registers_io_window->read8(0xc); }
|
|
u16 read_portsc1() { return m_registers_io_window->read16(0x10); }
|
|
u16 read_portsc2() { return m_registers_io_window->read16(0x12); }
|
|
|
|
void write_usbcmd(u16 value) { m_registers_io_window->write16(0, value); }
|
|
void write_usbsts(u16 value) { m_registers_io_window->write16(0x2, value); }
|
|
void write_usbintr(u16 value) { m_registers_io_window->write16(0x4, value); }
|
|
void write_frnum(u16 value) { m_registers_io_window->write16(0x6, value); }
|
|
void write_flbaseadd(u32 value) { m_registers_io_window->write32(0x8, value); }
|
|
void write_sofmod(u8 value) { m_registers_io_window->write8(0xc, value); }
|
|
void write_portsc1(u16 value) { m_registers_io_window->write16(0x10, value); }
|
|
void write_portsc2(u16 value) { m_registers_io_window->write16(0x12, value); }
|
|
|
|
virtual bool handle_irq(RegisterState const&) override;
|
|
|
|
ErrorOr<void> create_structures();
|
|
void setup_schedule();
|
|
|
|
void enqueue_qh(QueueHead* transfer_queue, QueueHead* anchor);
|
|
void dequeue_qh(QueueHead* transfer_queue);
|
|
|
|
size_t poll_transfer_queue(QueueHead& transfer_queue);
|
|
|
|
TransferDescriptor* create_transfer_descriptor(Pipe& pipe, PacketID direction, size_t data_len);
|
|
ErrorOr<void> create_chain(Pipe& pipe, PacketID direction, Ptr32<u8>& buffer_address, size_t max_size, size_t transfer_size, TransferDescriptor** td_chain, TransferDescriptor** last_td);
|
|
void free_descriptor_chain(TransferDescriptor* first_descriptor);
|
|
|
|
QueueHead* allocate_queue_head();
|
|
TransferDescriptor* allocate_transfer_descriptor();
|
|
|
|
void reset_port(u8);
|
|
|
|
NonnullOwnPtr<IOWindow> m_registers_io_window;
|
|
|
|
Spinlock m_schedule_lock;
|
|
|
|
OwnPtr<UHCIRootHub> m_root_hub;
|
|
OwnPtr<UHCIDescriptorPool<QueueHead>> m_queue_head_pool;
|
|
OwnPtr<UHCIDescriptorPool<TransferDescriptor>> m_transfer_descriptor_pool;
|
|
Vector<TransferDescriptor*> m_iso_td_list;
|
|
|
|
QueueHead* m_schedule_begin_anchor;
|
|
Array<QueueHead*, NUMBER_OF_INTERRUPT_QHS> m_interrupt_qh_anchor_arr;
|
|
QueueHead* m_ls_control_qh_anchor;
|
|
QueueHead* m_fs_control_qh_anchor;
|
|
// Always final queue in the schedule, may loop back to previous QH for bandwidth
|
|
// reclamation instead of actually terminating
|
|
QueueHead* m_bulk_qh_anchor;
|
|
|
|
OwnPtr<Memory::Region> m_framelist;
|
|
OwnPtr<Memory::Region> m_isochronous_transfer_pool;
|
|
|
|
// Bitfield containing whether a given port should signal a change in reset or not.
|
|
u8 m_port_reset_change_statuses { 0 };
|
|
|
|
// Bitfield containing whether a given port should signal a change in suspend or not.
|
|
u8 m_port_suspend_change_statuses { 0 };
|
|
};
|
|
}
|