mirror of
https://github.com/RGBCube/serenity
synced 2025-06-01 02:28:12 +00:00
9026598999
We now have these API's in <Kernel/Random.h>:
- get_fast_random_bytes(u8* buffer, size_t buffer_size)
- get_good_random_bytes(u8* buffer, size_t buffer_size)
- get_fast_random<T>()
- get_good_random<T>()
Internally they both use x86 RDRAND if available, otherwise they fall
back to the same LCG we had in RandomDevice all along.
The main purpose of this patch is to give kernel code a way to better
express its needs for random data.
Randomness is something that will require a lot more work, but this is
hopefully a step in the right direction.
548 lines
17 KiB
C++
548 lines
17 KiB
C++
#include "APIC.h"
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#include "Assertions.h"
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#include "IRQHandler.h"
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#include "PIC.h"
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#include "Process.h"
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#include <AK/Types.h>
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#include <Kernel/Arch/i386/CPU.h>
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#include <Kernel/KSyms.h>
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#include <Kernel/VM/MemoryManager.h>
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#include <LibC/mallocdefs.h>
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//#define PAGE_FAULT_DEBUG
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struct [[gnu::packed]] DescriptorTablePointer
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{
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u16 limit;
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void* address;
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};
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static DescriptorTablePointer s_idtr;
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static DescriptorTablePointer s_gdtr;
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static Descriptor s_idt[256];
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static Descriptor s_gdt[256];
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static IRQHandler* s_irq_handler[16];
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static Vector<u16>* s_gdt_freelist;
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static u16 s_gdt_length;
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u16 gdt_alloc_entry()
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{
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ASSERT(s_gdt_freelist);
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ASSERT(!s_gdt_freelist->is_empty());
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return s_gdt_freelist->take_last();
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}
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void gdt_free_entry(u16 entry)
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{
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s_gdt_freelist->append(entry);
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}
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extern "C" void handle_irq(RegisterDump);
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extern "C" void irq_common_asm_entry();
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#define GENERATE_IRQ_ASM_ENTRY(irq, isr_number) \
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extern "C" void irq_##irq##_asm_entry(); \
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asm(".globl irq_" #irq "_asm_entry\n" \
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"irq_" #irq "_asm_entry:\n" \
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" pushw $" #isr_number "\n" \
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" pushw $0\n" \
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" jmp irq_common_asm_entry\n");
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asm(
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".globl irq_common_asm_entry\n"
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"irq_common_asm_entry: \n"
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" pusha\n"
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" pushl %ds\n"
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" pushl %es\n"
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" pushl %fs\n"
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" pushl %gs\n"
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" pushl %ss\n"
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" mov $0x10, %ax\n"
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" mov %ax, %ds\n"
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" mov %ax, %es\n"
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" cld\n"
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" call handle_irq\n"
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" add $0x4, %esp\n" // "popl %ss"
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" popl %gs\n"
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" popl %fs\n"
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" popl %es\n"
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" popl %ds\n"
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" popa\n"
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" add $0x4, %esp\n"
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" iret\n");
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#define EH_ENTRY(ec, title) \
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extern "C" void title##_asm_entry(); \
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extern "C" void title##_handler(RegisterDump); \
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asm( \
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".globl " #title "_asm_entry\n" \
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"" #title "_asm_entry: \n" \
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" pusha\n" \
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" pushl %ds\n" \
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" pushl %es\n" \
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" pushl %fs\n" \
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" pushl %gs\n" \
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" pushl %ss\n" \
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" mov $0x10, %ax\n" \
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" mov %ax, %ds\n" \
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" mov %ax, %es\n" \
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" cld\n" \
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" call " #title "_handler\n" \
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" add $0x4, %esp \n" \
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" popl %gs\n" \
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" popl %fs\n" \
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" popl %es\n" \
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" popl %ds\n" \
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" popa\n" \
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" add $0x4, %esp\n" \
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" iret\n");
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#define EH_ENTRY_NO_CODE(ec, title) \
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extern "C" void title##_handler(RegisterDump); \
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extern "C" void title##_asm_entry(); \
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asm( \
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".globl " #title "_asm_entry\n" \
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"" #title "_asm_entry: \n" \
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" pushl $0x0\n" \
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" pusha\n" \
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" pushl %ds\n" \
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" pushl %es\n" \
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" pushl %fs\n" \
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" pushl %gs\n" \
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" pushl %ss\n" \
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" mov $0x10, %ax\n" \
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" mov %ax, %ds\n" \
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" mov %ax, %es\n" \
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" cld\n" \
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" call " #title "_handler\n" \
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" add $0x4, %esp\n" \
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" popl %gs\n" \
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" popl %fs\n" \
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" popl %es\n" \
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" popl %ds\n" \
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" popa\n" \
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" add $0x4, %esp\n" \
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" iret\n");
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static void dump(const RegisterDump& regs)
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{
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u16 ss;
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u32 esp;
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if (!current || current->process().is_ring0()) {
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ss = regs.ss;
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esp = regs.esp;
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} else {
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ss = regs.ss_if_crossRing;
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esp = regs.esp_if_crossRing;
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}
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kprintf("exception code: %04x (isr: %04x)\n", regs.exception_code, regs.isr_number);
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kprintf(" pc=%04x:%08x flags=%04x\n", (u16)regs.cs, regs.eip, (u16)regs.eflags);
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kprintf(" stk=%04x:%08x\n", ss, esp);
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kprintf(" ds=%04x es=%04x fs=%04x gs=%04x\n", (u16)regs.ds, (u16)regs.es, (u16)regs.fs, (u16)regs.gs);
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kprintf("eax=%08x ebx=%08x ecx=%08x edx=%08x\n", regs.eax, regs.ebx, regs.ecx, regs.edx);
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kprintf("ebp=%08x esp=%08x esi=%08x edi=%08x\n", regs.ebp, esp, regs.esi, regs.edi);
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if (current && current->process().validate_read((void*)regs.eip, 8)) {
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u8* codeptr = (u8*)regs.eip;
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kprintf("code: %02x %02x %02x %02x %02x %02x %02x %02x\n",
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codeptr[0],
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codeptr[1],
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codeptr[2],
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codeptr[3],
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codeptr[4],
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codeptr[5],
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codeptr[6],
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codeptr[7]);
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}
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}
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void handle_crash(RegisterDump& regs, const char* description, int signal)
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{
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if (!current) {
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kprintf("%s with !current\n", description);
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hang();
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}
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kprintf("\033[31;1mCRASH: %s. %s: %s(%u)\033[0m\n",
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description,
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current->process().is_ring0() ? "Kernel" : "Process",
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current->process().name().characters(),
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current->pid());
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dump(regs);
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if (current->process().is_ring0()) {
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kprintf("Oh shit, we've crashed in ring 0 :(\n");
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dump_backtrace();
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hang();
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}
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cli();
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current->process().crash(signal, regs.eip);
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}
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EH_ENTRY_NO_CODE(6, illegal_instruction);
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void illegal_instruction_handler(RegisterDump regs)
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{
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handle_crash(regs, "Illegal instruction", SIGILL);
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}
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EH_ENTRY_NO_CODE(0, divide_error);
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void divide_error_handler(RegisterDump regs)
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{
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handle_crash(regs, "Divide error", SIGFPE);
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}
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EH_ENTRY(13, general_protection_fault);
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void general_protection_fault_handler(RegisterDump regs)
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{
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handle_crash(regs, "General protection fault", SIGSEGV);
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}
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// 7: FPU not available exception
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EH_ENTRY_NO_CODE(7, fpu_exception);
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void fpu_exception_handler(RegisterDump)
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{
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// Just clear the TS flag. We've already restored the FPU state eagerly.
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// FIXME: It would be nice if we didn't have to do this at all.
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asm volatile("clts");
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}
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// 14: Page Fault
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EH_ENTRY(14, page_fault);
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void page_fault_handler(RegisterDump regs)
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{
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ASSERT(current);
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u32 fault_address;
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asm("movl %%cr2, %%eax"
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: "=a"(fault_address));
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u32 fault_page_directory;
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asm("movl %%cr3, %%eax"
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: "=a"(fault_page_directory));
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#ifdef PAGE_FAULT_DEBUG
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dbgprintf("%s(%u): ring%u %s page fault in PD=%x, %s V%08x\n",
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current->process().name().characters(),
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current->pid(),
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regs.cs & 3,
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regs.exception_code & 1 ? "PV" : "NP",
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fault_page_directory,
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regs.exception_code & 2 ? "write" : "read",
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fault_address);
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#endif
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#ifdef PAGE_FAULT_DEBUG
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dump(regs);
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#endif
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bool faulted_in_userspace = (regs.cs & 3) == 3;
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if (faulted_in_userspace && !MM.validate_user_stack(current->process(), VirtualAddress(regs.esp_if_crossRing))) {
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dbgprintf("Invalid stack pointer: %p\n", regs.esp_if_crossRing);
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handle_crash(regs, "Bad stack on page fault", SIGSTKFLT);
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ASSERT_NOT_REACHED();
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}
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auto response = MM.handle_page_fault(PageFault(regs.exception_code, VirtualAddress(fault_address)));
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if (response == PageFaultResponse::ShouldCrash) {
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if (current->has_signal_handler(SIGSEGV)) {
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current->send_urgent_signal_to_self(SIGSEGV);
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return;
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}
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kprintf("\033[31;1m%s(%u:%u) Unrecoverable page fault, %s%s%s address %p\033[0m\n",
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current->process().name().characters(),
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current->pid(),
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current->tid(),
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regs.exception_code & PageFaultFlags::ReservedBitViolation ? "reserved bit violation / " : "",
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regs.exception_code & PageFaultFlags::InstructionFetch ? "instruction fetch / " : "",
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regs.exception_code & PageFaultFlags::Write ? "write to" : "read from",
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fault_address);
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u32 malloc_scrub_pattern = explode_byte(MALLOC_SCRUB_BYTE);
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u32 free_scrub_pattern = explode_byte(FREE_SCRUB_BYTE);
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if ((fault_address & 0xffff0000) == (malloc_scrub_pattern & 0xffff0000)) {
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kprintf("\033[33;1mNote: Address %p looks like it may be uninitialized malloc() memory\033[0m\n", fault_address);
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} else if ((fault_address & 0xffff0000) == (free_scrub_pattern & 0xffff0000)) {
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kprintf("\033[33;1mNote: Address %p looks like it may be recently free()'d memory\033[0m\n", fault_address);
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} else if (fault_address < 4096) {
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kprintf("\033[33;1mNote: Address %p looks like a possible nullptr dereference\033[0m\n", fault_address);
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}
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handle_crash(regs, "Page Fault", SIGSEGV);
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} else if (response == PageFaultResponse::Continue) {
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#ifdef PAGE_FAULT_DEBUG
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dbgprintf("Continuing after resolved page fault\n");
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#endif
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} else {
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ASSERT_NOT_REACHED();
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}
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}
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#define EH(i, msg) \
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static void _exception##i() \
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{ \
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kprintf(msg "\n"); \
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u32 cr0, cr2, cr3, cr4; \
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asm("movl %%cr0, %%eax" \
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: "=a"(cr0)); \
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asm("movl %%cr2, %%eax" \
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: "=a"(cr2)); \
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asm("movl %%cr3, %%eax" \
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: "=a"(cr3)); \
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asm("movl %%cr4, %%eax" \
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: "=a"(cr4)); \
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kprintf("CR0=%x CR2=%x CR3=%x CR4=%x\n", cr0, cr2, cr3, cr4); \
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hang(); \
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}
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EH(1, "Debug exception")
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EH(2, "Unknown error")
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EH(3, "Breakpoint")
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EH(4, "Overflow")
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EH(5, "Bounds check")
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EH(8, "Double fault")
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EH(9, "Coprocessor segment overrun")
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EH(10, "Invalid TSS")
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EH(11, "Segment not present")
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EH(12, "Stack exception")
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EH(15, "Unknown error")
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EH(16, "Coprocessor error")
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static void write_raw_gdt_entry(u16 selector, u32 low, u32 high)
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{
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u16 i = (selector & 0xfffc) >> 3;
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s_gdt[i].low = low;
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s_gdt[i].high = high;
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if (i > s_gdt_length)
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s_gdtr.limit = (s_gdt_length + 1) * 8 - 1;
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}
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void write_gdt_entry(u16 selector, Descriptor& descriptor)
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{
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write_raw_gdt_entry(selector, descriptor.low, descriptor.high);
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}
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Descriptor& get_gdt_entry(u16 selector)
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{
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u16 i = (selector & 0xfffc) >> 3;
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return *(Descriptor*)(&s_gdt[i]);
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}
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void flush_gdt()
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{
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s_gdtr.address = s_gdt;
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s_gdtr.limit = (s_gdt_length * 8) - 1;
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asm("lgdt %0" ::"m"(s_gdtr)
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: "memory");
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}
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void gdt_init()
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{
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s_gdt_length = 5;
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s_gdt_freelist = new Vector<u16>();
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s_gdt_freelist->ensure_capacity(256);
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for (size_t i = s_gdt_length; i < 256; ++i)
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s_gdt_freelist->append(i * 8);
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s_gdt_length = 256;
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s_gdtr.address = s_gdt;
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s_gdtr.limit = (s_gdt_length * 8) - 1;
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write_raw_gdt_entry(0x0000, 0x00000000, 0x00000000);
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write_raw_gdt_entry(0x0008, 0x0000ffff, 0x00cf9a00);
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write_raw_gdt_entry(0x0010, 0x0000ffff, 0x00cf9200);
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write_raw_gdt_entry(0x0018, 0x0000ffff, 0x00cffa00);
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write_raw_gdt_entry(0x0020, 0x0000ffff, 0x00cff200);
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flush_gdt();
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asm volatile(
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"mov %%ax, %%ds\n"
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"mov %%ax, %%es\n"
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"mov %%ax, %%fs\n"
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"mov %%ax, %%gs\n"
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"mov %%ax, %%ss\n" ::"a"(0x10)
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: "memory");
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// Make sure CS points to the kernel code descriptor.
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asm volatile(
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"ljmpl $0x8, $sanity\n"
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"sanity:\n");
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}
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static void unimp_trap()
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{
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kprintf("Unhandled IRQ.");
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hang();
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}
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void register_irq_handler(u8 irq, IRQHandler& handler)
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{
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ASSERT(!s_irq_handler[irq]);
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s_irq_handler[irq] = &handler;
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}
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void unregister_irq_handler(u8 irq, IRQHandler& handler)
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{
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ASSERT(s_irq_handler[irq] == &handler);
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s_irq_handler[irq] = nullptr;
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}
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void register_interrupt_handler(u8 index, void (*f)())
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{
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s_idt[index].low = 0x00080000 | LSW((f));
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s_idt[index].high = ((u32)(f)&0xffff0000) | 0x8e00;
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flush_idt();
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}
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void register_user_callable_interrupt_handler(u8 index, void (*f)())
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{
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s_idt[index].low = 0x00080000 | LSW((f));
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s_idt[index].high = ((u32)(f)&0xffff0000) | 0xef00;
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flush_idt();
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}
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void flush_idt()
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{
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asm("lidt %0" ::"m"(s_idtr));
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}
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GENERATE_IRQ_ASM_ENTRY(0, 0x50)
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GENERATE_IRQ_ASM_ENTRY(1, 0x51)
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GENERATE_IRQ_ASM_ENTRY(2, 0x52)
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GENERATE_IRQ_ASM_ENTRY(3, 0x53)
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GENERATE_IRQ_ASM_ENTRY(4, 0x54)
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GENERATE_IRQ_ASM_ENTRY(5, 0x55)
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GENERATE_IRQ_ASM_ENTRY(6, 0x56)
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GENERATE_IRQ_ASM_ENTRY(7, 0x57)
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GENERATE_IRQ_ASM_ENTRY(8, 0x58)
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GENERATE_IRQ_ASM_ENTRY(9, 0x59)
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GENERATE_IRQ_ASM_ENTRY(10, 0x5a)
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GENERATE_IRQ_ASM_ENTRY(11, 0x5b)
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GENERATE_IRQ_ASM_ENTRY(12, 0x5c)
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GENERATE_IRQ_ASM_ENTRY(13, 0x5d)
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GENERATE_IRQ_ASM_ENTRY(14, 0x5e)
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GENERATE_IRQ_ASM_ENTRY(15, 0x5f)
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void idt_init()
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{
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s_idtr.address = s_idt;
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s_idtr.limit = 0x100 * 8 - 1;
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for (u8 i = 0xff; i > 0x10; --i)
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register_interrupt_handler(i, unimp_trap);
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register_interrupt_handler(0x00, divide_error_asm_entry);
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register_interrupt_handler(0x01, _exception1);
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register_interrupt_handler(0x02, _exception2);
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register_interrupt_handler(0x03, _exception3);
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register_interrupt_handler(0x04, _exception4);
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register_interrupt_handler(0x05, _exception5);
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register_interrupt_handler(0x06, illegal_instruction_asm_entry);
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register_interrupt_handler(0x07, fpu_exception_asm_entry);
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register_interrupt_handler(0x08, _exception8);
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register_interrupt_handler(0x09, _exception9);
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register_interrupt_handler(0x0a, _exception10);
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register_interrupt_handler(0x0b, _exception11);
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register_interrupt_handler(0x0c, _exception12);
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register_interrupt_handler(0x0d, general_protection_fault_asm_entry);
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register_interrupt_handler(0x0e, page_fault_asm_entry);
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register_interrupt_handler(0x0f, _exception15);
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|
register_interrupt_handler(0x10, _exception16);
|
|
|
|
register_interrupt_handler(0x50, irq_0_asm_entry);
|
|
register_interrupt_handler(0x51, irq_1_asm_entry);
|
|
register_interrupt_handler(0x52, irq_2_asm_entry);
|
|
register_interrupt_handler(0x53, irq_3_asm_entry);
|
|
register_interrupt_handler(0x54, irq_4_asm_entry);
|
|
register_interrupt_handler(0x55, irq_5_asm_entry);
|
|
register_interrupt_handler(0x56, irq_6_asm_entry);
|
|
register_interrupt_handler(0x57, irq_7_asm_entry);
|
|
register_interrupt_handler(0x58, irq_8_asm_entry);
|
|
register_interrupt_handler(0x59, irq_9_asm_entry);
|
|
register_interrupt_handler(0x5a, irq_10_asm_entry);
|
|
register_interrupt_handler(0x5b, irq_11_asm_entry);
|
|
register_interrupt_handler(0x5c, irq_12_asm_entry);
|
|
register_interrupt_handler(0x5d, irq_13_asm_entry);
|
|
register_interrupt_handler(0x5e, irq_14_asm_entry);
|
|
register_interrupt_handler(0x5f, irq_15_asm_entry);
|
|
|
|
for (u8 i = 0; i < 16; ++i) {
|
|
s_irq_handler[i] = nullptr;
|
|
}
|
|
|
|
flush_idt();
|
|
}
|
|
|
|
void load_task_register(u16 selector)
|
|
{
|
|
asm("ltr %0" ::"r"(selector));
|
|
}
|
|
|
|
void handle_irq(RegisterDump regs)
|
|
{
|
|
ASSERT(regs.isr_number >= 0x50 && regs.isr_number <= 0x5f);
|
|
u8 irq = (u8)(regs.isr_number - 0x50);
|
|
if (s_irq_handler[irq])
|
|
s_irq_handler[irq]->handle_irq();
|
|
PIC::eoi(irq);
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
void __assertion_failed(const char* msg, const char* file, unsigned line, const char* func)
|
|
{
|
|
asm volatile("cli");
|
|
kprintf("ASSERTION FAILED: %s\n%s:%u in %s\n", msg, file, line, func);
|
|
dump_backtrace();
|
|
asm volatile("hlt");
|
|
for (;;)
|
|
;
|
|
}
|
|
#endif
|
|
|
|
void sse_init()
|
|
{
|
|
asm volatile(
|
|
"mov %cr0, %eax\n"
|
|
"andl $0xfffffffb, %eax\n"
|
|
"orl $0x2, %eax\n"
|
|
"mov %eax, %cr0\n"
|
|
"mov %cr4, %eax\n"
|
|
"orl $0x600, %eax\n"
|
|
"mov %eax, %cr4\n");
|
|
}
|
|
|
|
bool g_cpu_supports_nx;
|
|
bool g_cpu_supports_pae;
|
|
bool g_cpu_supports_pge;
|
|
bool g_cpu_supports_rdrand;
|
|
bool g_cpu_supports_smep;
|
|
bool g_cpu_supports_sse;
|
|
bool g_cpu_supports_tsc;
|
|
bool g_cpu_supports_umip;
|
|
|
|
void detect_cpu_features()
|
|
{
|
|
CPUID processor_info(0x1);
|
|
g_cpu_supports_pae = (processor_info.edx() & (1 << 6));
|
|
g_cpu_supports_pge = (processor_info.edx() & (1 << 13));
|
|
g_cpu_supports_sse = (processor_info.edx() & (1 << 25));
|
|
g_cpu_supports_tsc = (processor_info.edx() & (1 << 4));
|
|
g_cpu_supports_rdrand = (processor_info.ecx() & (1 << 30));
|
|
|
|
CPUID extended_processor_info(0x80000001);
|
|
g_cpu_supports_nx = (extended_processor_info.edx() & (1 << 20));
|
|
|
|
CPUID extended_features(0x7);
|
|
g_cpu_supports_smep = (extended_features.ebx() & (1 << 7));
|
|
g_cpu_supports_umip = (extended_features.ecx() & (1 << 2));
|
|
}
|