mirror of
https://github.com/RGBCube/serenity
synced 2025-05-20 14:05:08 +00:00
9132596b8e
This will somwhat help unify them also under the same SysFS directory in the commit. Also, it feels much more like this change reflects the reality that both ACPI and the BIOS are part of the firmware on x86 computers.
441 lines
17 KiB
C++
441 lines
17 KiB
C++
/*
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* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <AK/ByteReader.h>
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#include <AK/HashTable.h>
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#include <Kernel/API/KResult.h>
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#include <Kernel/Bus/PCI/Access.h>
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#include <Kernel/Debug.h>
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#include <Kernel/Firmware/ACPI/Definitions.h>
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#include <Kernel/IO.h>
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#include <Kernel/Memory/MemoryManager.h>
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#include <Kernel/Memory/Region.h>
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#include <Kernel/Sections.h>
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namespace Kernel::PCI {
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#define PCI_MMIO_CONFIG_SPACE_SIZE 4096
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#define MEMORY_RANGE_PER_BUS (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS)
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static Access* s_access;
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Access& Access::the()
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{
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if (s_access == nullptr) {
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VERIFY_NOT_REACHED(); // We failed to initialize the PCI subsystem, so stop here!
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}
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return *s_access;
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}
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bool Access::is_initialized()
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{
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return (s_access != nullptr);
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}
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UNMAP_AFTER_INIT bool Access::initialize_for_memory_access(PhysicalAddress mcfg_table)
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{
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if (Access::is_initialized())
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return false;
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InterruptDisabler disabler;
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auto* access = new Access(Access::AccessType::Memory);
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if (!access->scan_pci_domains(mcfg_table))
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return false;
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access->rescan_hardware();
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dbgln_if(PCI_DEBUG, "PCI: MMIO access initialised.");
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return true;
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}
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UNMAP_AFTER_INIT bool Access::scan_pci_domains(PhysicalAddress mcfg_table)
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{
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auto checkup_region_or_error = MM.allocate_kernel_region(mcfg_table.page_base(), (PAGE_SIZE * 2), "PCI MCFG Checkup", Memory::Region::Access::ReadWrite);
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if (checkup_region_or_error.is_error())
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return false;
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dbgln_if(PCI_DEBUG, "PCI: Checking MCFG Table length to choose the correct mapping size");
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auto* sdt = (ACPI::Structures::SDTHeader*)checkup_region_or_error.value()->vaddr().offset(mcfg_table.offset_in_page()).as_ptr();
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u32 length = sdt->length;
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u8 revision = sdt->revision;
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dbgln("PCI: MCFG, length: {}, revision: {}", length, revision);
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auto mcfg_region_or_error = MM.allocate_kernel_region(mcfg_table.page_base(), Memory::page_round_up(length) + PAGE_SIZE, "PCI Parsing MCFG", Memory::Region::Access::ReadWrite);
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if (mcfg_region_or_error.is_error())
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return false;
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auto& mcfg = *(ACPI::Structures::MCFG*)mcfg_region_or_error.value()->vaddr().offset(mcfg_table.offset_in_page()).as_ptr();
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dbgln_if(PCI_DEBUG, "PCI: Checking MCFG @ {}, {}", VirtualAddress(&mcfg), mcfg_table);
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for (u32 index = 0; index < ((mcfg.header.length - sizeof(ACPI::Structures::MCFG)) / sizeof(ACPI::Structures::PCI_MMIO_Descriptor)); index++) {
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u8 start_bus = mcfg.descriptors[index].start_pci_bus;
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u8 end_bus = mcfg.descriptors[index].end_pci_bus;
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u32 lower_addr = mcfg.descriptors[index].base_addr;
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auto result = m_domains.set(index, { PhysicalAddress(lower_addr), start_bus, end_bus });
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VERIFY(result == AK::HashSetResult::InsertedNewEntry);
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dmesgln("PCI: New PCI domain @ {}, PCI buses ({}-{})", PhysicalAddress { lower_addr }, start_bus, end_bus);
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}
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VERIFY(m_domains.contains(0));
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dmesgln("PCI: MMIO domain: {}", m_domains.size());
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return true;
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}
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UNMAP_AFTER_INIT bool Access::initialize_for_io_access()
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{
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if (Access::is_initialized()) {
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return false;
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}
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auto* access = new Access(Access::AccessType::IO);
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access->rescan_hardware();
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dbgln_if(PCI_DEBUG, "PCI: IO access initialised.");
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return true;
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}
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UNMAP_AFTER_INIT Access::Access(AccessType access_type)
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: m_enumerated_buses(256, false)
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, m_access_type(access_type)
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{
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if (access_type == AccessType::IO)
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dmesgln("PCI: Using I/O instructions for PCI configuration space access");
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else
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dmesgln("PCI: Using memory access for PCI configuration space accesses");
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s_access = this;
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}
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Optional<PhysicalAddress> Access::determine_memory_mapped_bus_base_address(u32 domain, u8 bus) const
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{
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auto chosen_domain = m_domains.get(domain);
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if (!chosen_domain.has_value())
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return {};
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if (!(chosen_domain.value().start_bus() <= bus && bus <= chosen_domain.value().end_bus()))
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return {};
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return chosen_domain.value().paddr().offset(MEMORY_RANGE_PER_BUS * (bus - chosen_domain.value().start_bus()));
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}
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void Access::map_bus_region(u32 domain, u8 bus)
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{
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VERIFY(m_access_lock.is_locked());
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if (m_mapped_bus == bus && m_mapped_bus_region)
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return;
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auto bus_base_address = determine_memory_mapped_bus_base_address(domain, bus);
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// FIXME: Find a way to propagate error from here.
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if (!bus_base_address.has_value())
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VERIFY_NOT_REACHED();
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auto region_or_error = MM.allocate_kernel_region(bus_base_address.value(), MEMORY_RANGE_PER_BUS, "PCI ECAM", Memory::Region::Access::ReadWrite);
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// FIXME: Find a way to propagate error from here.
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if (region_or_error.is_error())
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VERIFY_NOT_REACHED();
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m_mapped_bus_region = region_or_error.release_value();
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m_mapped_bus = bus;
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dbgln_if(PCI_DEBUG, "PCI: New PCI ECAM Mapped region for bus {} @ {} {}", bus, m_mapped_bus_region->vaddr(), m_mapped_bus_region->physical_page(0)->paddr());
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}
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VirtualAddress Access::get_device_configuration_memory_mapped_space(Address address)
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{
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VERIFY(m_access_lock.is_locked());
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dbgln_if(PCI_DEBUG, "PCI: Getting device configuration space for {}", address);
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map_bus_region(address.domain(), address.bus());
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return m_mapped_bus_region->vaddr().offset(PCI_MMIO_CONFIG_SPACE_SIZE * address.function() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE) * address.device());
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}
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u8 Access::io_read8_field(Address address, u32 field)
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{
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MutexLocker lock(m_access_lock);
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dbgln_if(PCI_DEBUG, "PCI: IO Reading 8-bit field {:#08x} for {}", field, address);
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IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
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return IO::in8(PCI_VALUE_PORT + (field & 3));
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}
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u16 Access::io_read16_field(Address address, u32 field)
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{
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MutexLocker lock(m_access_lock);
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dbgln_if(PCI_DEBUG, "PCI: IO Reading 16-bit field {:#08x} for {}", field, address);
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IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
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return IO::in16(PCI_VALUE_PORT + (field & 2));
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}
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u32 Access::io_read32_field(Address address, u32 field)
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{
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MutexLocker lock(m_access_lock);
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dbgln_if(PCI_DEBUG, "PCI: IO Reading 32-bit field {:#08x} for {}", field, address);
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IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
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return IO::in32(PCI_VALUE_PORT);
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}
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void Access::io_write8_field(Address address, u32 field, u8 value)
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{
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MutexLocker lock(m_access_lock);
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dbgln_if(PCI_DEBUG, "PCI: IO Writing to 8-bit field {:#08x}, value={:#02x} for {}", field, value, address);
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IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
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IO::out8(PCI_VALUE_PORT + (field & 3), value);
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}
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void Access::io_write16_field(Address address, u32 field, u16 value)
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{
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MutexLocker lock(m_access_lock);
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dbgln_if(PCI_DEBUG, "PCI: IO Writing to 16-bit field {:#08x}, value={:#02x} for {}", field, value, address);
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IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
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IO::out16(PCI_VALUE_PORT + (field & 2), value);
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}
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void Access::io_write32_field(Address address, u32 field, u32 value)
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{
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MutexLocker lock(m_access_lock);
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dbgln_if(PCI_DEBUG, "PCI: IO Writing to 32-bit field {:#08x}, value={:#02x} for {}", field, value, address);
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IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
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IO::out32(PCI_VALUE_PORT, value);
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}
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u8 Access::memory_read8_field(Address address, u32 field)
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{
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MutexLocker lock(m_access_lock);
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VERIFY(field <= 0xfff);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 8-bit field {:#08x} for {}", field, address);
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return *((volatile u8*)(get_device_configuration_memory_mapped_space(address).get() + (field & 0xfff)));
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}
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u16 Access::memory_read16_field(Address address, u32 field)
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{
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MutexLocker lock(m_access_lock);
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VERIFY(field < 0xfff);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 16-bit field {:#08x} for {}", field, address);
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u16 data = 0;
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ByteReader::load<u16>(get_device_configuration_memory_mapped_space(address).offset(field & 0xfff).as_ptr(), data);
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return data;
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}
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u32 Access::memory_read32_field(Address address, u32 field)
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{
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MutexLocker lock(m_access_lock);
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VERIFY(field <= 0xffc);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 32-bit field {:#08x} for {}", field, address);
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u32 data = 0;
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ByteReader::load<u32>(get_device_configuration_memory_mapped_space(address).offset(field & 0xfff).as_ptr(), data);
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return data;
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}
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void Access::memory_write8_field(Address address, u32 field, u8 value)
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{
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MutexLocker lock(m_access_lock);
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VERIFY(field <= 0xfff);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 8-bit field {:#08x}, value={:#02x} for {}", field, value, address);
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*((volatile u8*)(get_device_configuration_memory_mapped_space(address).get() + (field & 0xfff))) = value;
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}
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void Access::memory_write16_field(Address address, u32 field, u16 value)
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{
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MutexLocker lock(m_access_lock);
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VERIFY(field < 0xfff);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 16-bit field {:#08x}, value={:#02x} for {}", field, value, address);
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ByteReader::store<u16>(get_device_configuration_memory_mapped_space(address).offset(field & 0xfff).as_ptr(), value);
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}
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void Access::memory_write32_field(Address address, u32 field, u32 value)
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{
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MutexLocker lock(m_access_lock);
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VERIFY(field <= 0xffc);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 32-bit field {:#08x}, value={:#02x} for {}", field, value, address);
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ByteReader::store<u32>(get_device_configuration_memory_mapped_space(address).offset(field & 0xfff).as_ptr(), value);
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}
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void Access::write8_field(Address address, u32 field, u8 value)
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{
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switch (m_access_type) {
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case AccessType::IO:
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io_write8_field(address, field, value);
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return;
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case AccessType::Memory:
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memory_write8_field(address, field, value);
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return;
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}
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VERIFY_NOT_REACHED();
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}
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void Access::write16_field(Address address, u32 field, u16 value)
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{
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switch (m_access_type) {
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case AccessType::IO:
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io_write16_field(address, field, value);
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return;
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case AccessType::Memory:
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memory_write16_field(address, field, value);
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return;
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}
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VERIFY_NOT_REACHED();
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}
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void Access::write32_field(Address address, u32 field, u32 value)
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{
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switch (m_access_type) {
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case AccessType::IO:
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io_write32_field(address, field, value);
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return;
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case AccessType::Memory:
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memory_write32_field(address, field, value);
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return;
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}
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VERIFY_NOT_REACHED();
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}
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u8 Access::read8_field(Address address, u32 field)
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{
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switch (m_access_type) {
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case AccessType::IO:
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return io_read8_field(address, field);
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case AccessType::Memory:
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return memory_read8_field(address, field);
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}
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VERIFY_NOT_REACHED();
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}
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u16 Access::read16_field(Address address, u32 field)
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{
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switch (m_access_type) {
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case AccessType::IO:
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return io_read16_field(address, field);
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case AccessType::Memory:
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return memory_read16_field(address, field);
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}
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VERIFY_NOT_REACHED();
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}
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u32 Access::read32_field(Address address, u32 field)
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{
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switch (m_access_type) {
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case AccessType::IO:
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return io_read32_field(address, field);
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case AccessType::Memory:
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return memory_read32_field(address, field);
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}
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VERIFY_NOT_REACHED();
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}
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UNMAP_AFTER_INIT void Access::rescan_hardware()
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{
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MutexLocker locker(m_scan_lock);
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VERIFY(m_physical_ids.is_empty());
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if (m_access_type == AccessType::IO) {
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dbgln_if(PCI_DEBUG, "PCI: IO enumerating hardware");
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// First scan bus 0. Find any device on that bus, and if it's a PCI-to-PCI
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// bridge, recursively scan it too.
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m_enumerated_buses.set(0, true);
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enumerate_bus(-1, 0, true);
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// Handle Multiple PCI host bridges on slot 0, device 0.
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// If we happen to miss some PCI buses because they are not reachable through
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// recursive PCI-to-PCI bridges starting from bus 0, we might find them here.
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if ((read8_field(Address(), PCI_HEADER_TYPE) & 0x80) != 0) {
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for (int bus = 1; bus < 256; ++bus) {
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if (read16_field(Address(0, 0, 0, bus), PCI_VENDOR_ID) == PCI_NONE)
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continue;
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if (read16_field(Address(0, 0, 0, bus), PCI_CLASS) != 0x6)
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continue;
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if (m_enumerated_buses.get(bus))
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continue;
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enumerate_bus(-1, bus, false);
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m_enumerated_buses.set(bus, true);
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}
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}
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return;
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}
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VERIFY(m_access_type == AccessType::Memory);
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for (u32 domain = 0; domain < m_domains.size(); domain++) {
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dbgln_if(PCI_DEBUG, "PCI: Scan memory mapped domain {}", domain);
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// Single PCI host controller.
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if ((read8_field(Address(domain), PCI_HEADER_TYPE) & 0x80) == 0) {
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enumerate_bus(-1, 0, true);
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return;
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}
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// Multiple PCI host controllers.
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for (u8 function = 0; function < 8; ++function) {
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if (read16_field(Address(domain, 0, 0, function), PCI_VENDOR_ID) == PCI_NONE)
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break;
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enumerate_bus(-1, function, false);
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}
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}
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}
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UNMAP_AFTER_INIT Optional<u8> Access::get_capabilities_pointer(Address address)
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{
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dbgln_if(PCI_DEBUG, "PCI: Getting capabilities pointer for {}", address);
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if (read16_field(address, PCI_STATUS) & (1 << 4)) {
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dbgln_if(PCI_DEBUG, "PCI: Found capabilities pointer for {}", address);
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return read8_field(address, PCI_CAPABILITIES_POINTER);
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}
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dbgln_if(PCI_DEBUG, "PCI: No capabilities pointer for {}", address);
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return {};
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}
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UNMAP_AFTER_INIT Vector<Capability> Access::get_capabilities(Address address)
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{
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dbgln_if(PCI_DEBUG, "PCI: Getting capabilities for {}", address);
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auto capabilities_pointer = get_capabilities_pointer(address);
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if (!capabilities_pointer.has_value()) {
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dbgln_if(PCI_DEBUG, "PCI: No capabilities for {}", address);
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return {};
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}
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Vector<Capability> capabilities;
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auto capability_pointer = capabilities_pointer.value();
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while (capability_pointer != 0) {
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dbgln_if(PCI_DEBUG, "PCI: Reading in capability at {:#02x} for {}", capability_pointer, address);
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u16 capability_header = read16_field(address, capability_pointer);
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u8 capability_id = capability_header & 0xff;
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capabilities.append({ address, capability_id, capability_pointer });
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capability_pointer = capability_header >> 8;
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}
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return capabilities;
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}
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UNMAP_AFTER_INIT void Access::enumerate_functions(int type, u8 bus, u8 device, u8 function, bool recursive)
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{
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dbgln_if(PCI_DEBUG, "PCI: Enumerating function type={}, bus={}, device={}, function={}", type, bus, device, function);
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Address address(0, bus, device, function);
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auto read_type = (read8_field(address, PCI_CLASS) << 8u) | read8_field(address, PCI_SUBCLASS);
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if (type == -1 || type == read_type) {
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m_physical_ids.append(PhysicalID { address, { read16_field(address, PCI_VENDOR_ID), read16_field(address, PCI_DEVICE_ID) }, get_capabilities(address) });
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}
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if (read_type == PCI_TYPE_BRIDGE && recursive && (!m_enumerated_buses.get(read8_field(address, PCI_SECONDARY_BUS)))) {
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u8 secondary_bus = read8_field(address, PCI_SECONDARY_BUS);
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dbgln_if(PCI_DEBUG, "PCI: Found secondary bus: {}", secondary_bus);
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VERIFY(secondary_bus != bus);
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m_enumerated_buses.set(secondary_bus, true);
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enumerate_bus(type, secondary_bus, recursive);
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}
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}
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UNMAP_AFTER_INIT void Access::enumerate_device(int type, u8 bus, u8 device, bool recursive)
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{
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dbgln_if(PCI_DEBUG, "PCI: Enumerating device type={}, bus={}, device={}", type, bus, device);
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Address address(0, bus, device, 0);
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if (read16_field(address, PCI_VENDOR_ID) == PCI_NONE)
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return;
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enumerate_functions(type, bus, device, 0, recursive);
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if (!(read8_field(address, PCI_HEADER_TYPE) & 0x80))
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return;
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for (u8 function = 1; function < 8; ++function) {
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Address address(0, bus, device, function);
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if (read16_field(address, PCI_VENDOR_ID) != PCI_NONE)
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enumerate_functions(type, bus, device, function, recursive);
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|
}
|
|
}
|
|
|
|
UNMAP_AFTER_INIT void Access::enumerate_bus(int type, u8 bus, bool recursive)
|
|
{
|
|
dbgln_if(PCI_DEBUG, "PCI: Enumerating bus type={}, bus={}", type, bus);
|
|
for (u8 device = 0; device < 32; ++device)
|
|
enumerate_device(type, bus, device, recursive);
|
|
}
|
|
|
|
void Access::fast_enumerate(Function<void(Address, ID)>& callback) const
|
|
{
|
|
MutexLocker locker(m_scan_lock);
|
|
VERIFY(!m_physical_ids.is_empty());
|
|
for (auto& physical_id : m_physical_ids) {
|
|
callback(physical_id.address(), physical_id.id());
|
|
}
|
|
}
|
|
|
|
PhysicalID Access::get_physical_id(Address address) const
|
|
{
|
|
for (auto physical_id : m_physical_ids) {
|
|
if (physical_id.address().domain() == address.domain()
|
|
&& physical_id.address().bus() == address.bus()
|
|
&& physical_id.address().device() == address.device()
|
|
&& physical_id.address().function() == address.function()) {
|
|
return physical_id;
|
|
}
|
|
}
|
|
VERIFY_NOT_REACHED();
|
|
}
|
|
|
|
}
|